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Part: AM53CF94KC
Category:
Description: Enhanced Scsi-2 Controller ( Esc )
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM53CF94KC datasheet File size : 342 kB
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D
PRELIMINARY
Am53CF94/Am53CF96
Enhanced SCSI-2 Controller (ESC)
ISTINCTIVE CHARACTERISTICS
s s s s s s s s s s s s s s s Pin/function compatible with Emulex FAS216/236 AMD's Patented programmable GLITCH EATERTM Circuitry on REQ and ACK inputs 10 Mbytes/s synchronous Fast SCSI transfer rate 20 Mbytes/s DMA transfer rate 16-Bit DMA interface plus 2 bits of parity Flexible three bus architecture Single-ended SCSI bus supported by Am53CF94 Differential SCSI bus supported by Am53CF96 Selection of multiplexed or non-multiplexed address and data bus High current drivers (48 mA) for direct connection to the single-ended SCSI bus Supports Disconnect and Reselect commands Supports burst mode DMA operation with a threshold of eight Supports 3-byte tagged-queueing as per the SCSI-2 specification Supports group 2 and 5 command recognition as per the SCSI-2 specification Advanced CMOS process for lower power consumption s s s s s s s s s s s s s s s
Advanced Micro Devices
AMD's exclusive programmable power-down feature 24-Bit extended transfer counter allows for data block transfer of up to 16 Mbytes Independently programmable 3-byte message and group 2 identification Additional check for ID message during bus-initiated Select with ATN Reselection has QTAG features of ATN3 Access FIFO Command Delayed enable signal for differential drivers avoid contention on SCSI differential lines Programmable Active Negation on REQ, ACK and Data lines Register programmable control of assertion/ deassertion delay for REQ and ACK lines Part-unique ID code Am53CF94 available in 84-pin PLCC package Am53CF96 available in 100-pin PQFP package Am53CF94 available in 3.3 V version Supports clock operating frequencies from 10 MHz40 MHz Supports Scatter-Gather or Back-to-Back synchronous data transfers
GENERAL DESCRIPTION
The Enhanced SCSI-2 Controller (ESC) was designed to support Fast SCSI-2 transfer rates of up to 10 Mbytes/s in synchronous mode and up to 7 Mbytes/s in the asynchronous mode. The ESC is downward compatible with the Am53C94/96, combining its functionality with features such as Fast SCSI, programmable Active Negation, a 24-bit transfer counter, and a part-unique ID code containing manufacturer and serial # information. AMD's proprietary features such as power-down mode for SCSI transceivers, programmable GLITCH EATER, and extended Target command set are also included for improved product performance. The Enhanced SCSI-2 Controller (ESC) has a flexible three bus architecture. The ESC has a 16-bit DMA interface, an 8-bit host data interface and an 8-bit SCSI data interface. The ESC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in response to a single command from the host. Selection, reselection, information transfer and disconnection commands are directly supported. The 16-byte-internal FIFO further assists in minimizing host involvement. The FIFO provides a temporary storage for all command, data, status and message bytes as they are transferred between the 16-bit host data bus and the 8-bit SCSI data bus. During DMA operations the FIFO acts as a buffer to allow greater latency in the DMA channel. This permits the DMA channel to be suspended for higher priority operations such as DRAM refresh or reception of an ISDN packet. Parity on the DMA bus is optional. Parity can either be generated and checked or it can be simply passed through. The Target command set for the Am53CF94/96 includes an additional command, the Access FIFO command, to allow the host or DMA controller to remove remaining FIFO data following the host's issuance of a Target abort DMA command or following an abort due to
Publication# 17348 Rev. B Issue Date: May 1993 Amendment /0
This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
AMD
PRELIMINARY removing glitches that may cause system failure. The GLITCH EATER Circuitry is implemented on the ACK and REQ lines since they are most susceptible to electrical anomalies such as reflections and voltage spikes. Such signal inconsistencies can trigger false REQ/ACK handshaking, false data transfers, addition of random data, and double clocking. AMD's GLITCH EATER Circuitry therefore maintains system performance and improves reliability. The following diagram illustrates this circuit's operation. The Am53CF94 is also available in a 3.3 V version.
parity error. This command facilitates data recovery and thereby minimizes the need to re-transmit data. AMD's exclusive power-down feature can be enabled to help reduce power consumption during the chip's sleep mode. The receivers on the SCSI bus may be turned off to eliminate current that may flow because termination power (~3 V) is close to the trip point of the input buffers. The patented GLITCH EATER Circuitry in the Enhanced SCSI-2 Controller can be programmed to filter glitches with widths up to 35 ns. It is designed to dramatically increase system reliability by detecting and
GLITCH EATER Circuitry in SCSI Environment
SCSI Environment
Device without the GLITCH EATER Circuit
Glitch Window
AMD's Device with the GLITCH EATER Circuit
Note: The Glitch Window is programmable via Control Register Four (0DH), bits 6 & 7. Window may be set to 35 ns (max). Default setting is 12 ns (single-ended).
17348B-1
SYSTEM BLOCK DIAGRAM
4 CPU 16 8
Addr 9 Data Am53CF94/96 9 16 SCSI Control SCSI Data
DMA
16
DMA
Memory
16
17348B-2
2
Am53CF94/Am53CF96
PRELIMINARY
AMD
SYSTEM BUS MODE DIAGRAMS
BUSMD 1 BUSMD 0 DMAWR WR RD Address Bus 8-Bit Data Bus DMA 70 DACK DREQ Host Processor Bus Controller
Am53CF94/96
A 30
DMA Controller
17348B-3
Bus Mode 0 Single Bus Architecture: 8-Bit DMA, 8-Bit Processor
VDD
BUSMD 1 BUSMD 0
DMAWR WR RD Address Bus A 30 Data Bus DMA 150 Host Processor Bus Controller
Am53CF94/96
DACK
DREQ
16
8
DMA Controller
Bus Mode 1 Single Bus Architecture: 16-Bit DMA, 8-Bit Processor
17348B-4
Am53CF94/Am53CF96
3
AMD
PRELIMINARY
SYSTEM BUS MODE DIAGRAMS
VDD
BUSMD 1 BUSMD 0
WR RD ALE 8-Bit Data Bus AD 70 Host Processor
Am53CF94/96
16-Bit Data Bus DMA 150 AS0 BHE DMARD DMAWR DREQ DACK DMA Controller
Bus Mode 2 Dual Bus Architecture: 16-Bit DMA with Byte Control, 8-Bit Multiplexed Processor Address Data
17348B-5
VDD
BUSMD 1 BUSMD 0
WR RD Address Bus A 30 8-Bit Data Bus AD 70 Host Processor
Am53CF94/96
16-Bit Data Bus DMA 150 DMAWR DREQ DACK DMA Controller
Bus Mode 3 Dual Bus Architecture: 16-Bit DMA, 8-Bit Processor 4 Am53CF94/Am53CF96
17348B-6
PRELIMINARY
AMD
BLOCK DIAGRAM
Data Tranceivers
18 DMA 15-0 DMAP1-0 DMA Control 4 Bus Interface Unit 8
16 x 9 FIFO (including parity)
18
9
SCSI Bus Data + Parity (Single Ended) SCSI Bus Data + Parity Direction Control
Parity Logic
9
AD 7-0 Host Control CS BUSMD1-0 DFMODE CLK RESET 6
MUX
SCSI Control
8
Register B ank
S Main equencer 9 7 SCSI Control D SCSI Control irection Control
8 S SCSI equencer
17348B-7
Am53CF94/Am53CF96
5
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