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Part: AM79C90PCTR
Category:
Communication
-> Network
-> Ethernet/DS1/E1 (T1/E1)
Description: CMOS Local Area Network Controller For Ethernet ( C-lance )
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM79C90PCTR datasheet File size : 1108 kB
Request For quote: Find where to buy AM79C90PCTR
Datasheet text preview:
PRELIMINARY
Am79C90
CMOS Local Area Network Controller for Ethernet (C-LANCE)
DISTINCTIVE CHARACTERISTICS
s Compatible with Ethernet and IEEE 802.3 10BASE-5 Type A, and 10BASE-2 Type B, "Cheapernet," 10BASE-T s Easily interfaced with 80x86, 680x0, Am29000®, Z8000TM microprocessors s On-board DMA and buffer management, 64-byte Receive, 48-byte Transmit FIFOs s 24-bit-wide linear addressing (Bus Master Mode) s Network and packet error reporting s Back-to-back packet reception with as little as 0.5 µs interframe spacing s Diagnostic Routines -- Internal/external loopback -- CRC logic check -- Time domain reflectometer s Low power consumption for power-sensitive applications s Completely software- and hardware-compatible with AMD's LANCE device (Am7990) (see Appendix A)
GENERAL DESCRIPTION
The Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) is a 48-pin VLSI device designed to greatly simplify interfacing a microcomputer or minicomputer to an IEEE 802.3/Ethernet Local Area N e t wo r k . The C-LANCE, in conjunction with the Am7992B Serial Interface Adapter (SIA), Am7996 or Am79C98 and Am79C100 Transceiver, and closely coupled local memory and microprocessor, is intended to provide the user with a complete interface module for an Ethernet network. The Am79C90 is designed using a scalable CMOS technology and is compatible with a variety of microprocessors. On-board DMA, advanced buffer management, and extensive error reporting and d i a g n o s t i c s facilitate design and improve system performance.
BLOCK DIAGRAM
DAL15:0 A23:16 Parallel Bus Interface DMA/Data Path Control Microprogram Store
INTR HOLD HLDA ALE/AS CS ADR DAS DALO DALI READ BM0/BYTE BM1/BUSAKO READY RESET
Local CPU Interface
C-LANCE/ CPU Control Bus Interface
Station Address Detection
Retry Logic
Serial I/O Interface
RX RCLK TX TCLK CLSN TENA RENA
17881C-1
Publication# 17881 Rev: C Amendment/0 Issue Date: January 1998
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Am7992B SIA Interface
1
AMD
PRELIMINARY
RELATED AMD PRODUCTS
Part No. Am7996 Am79C100 Am79C900 Am79C940 Am79C960 Am79C961 Am79C965 Am79C970 Am79C974 Am79C98 Am79C981 Am79C987 Description IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Twisted-Pair Ethernet Transceiver Plus (TPEX+) Integrated Local Area Communications ControllerTM (ILACCTM) Media Access Controller for Ethernet (MACETM) PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) PCnet-ISA Single-Chip Ethernet Controller (with Microsoft® Plug n' Play support) PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386DX, 486 and VL buses) PCnet-PCI Single-Chip Ethernet Controller (for PCI bus) PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems Twisted-Pair Ethernet Transceiver (TPEX) Integrated Multiport Repeater PlusTM (IMR+TM) Hardware Implemented Management Information BaseTM (HIMIBTM)
CONNECTION DIAGRAMS DIP
VSS DAL7 DAL6 DAL5 DAL4 DAL3 DAL2 DAL1 DAL0 READ INTR DALI DALO DAS BM0/BYTE BM1/BUSAKO HOLD/BUSRQ ALE/AS HLDA CS ADR READY RESET VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD DAL9 READ INTR DAL0 DAL10 DAL11 DAL12 DAL13 DAL14 DAL15 A16 A17 A18 A19 A20 A21 A22 A23 RX RENA TX CLSN RCLK TENA TCLK
17881B-3
PLCC
NC DAS BM0/BYTE
BM1/BUSRQ
DAL8 DALI DALO NC
HOLD/BUSRQ ALE/AS HLDA
DAL1
NC
NC
98765432 NC NC DAL2 DAL3 DAL4 DAL5 DAL6 DAL7 VSS VDD DAL8 DAL9 DAL10 DAL11 DAL12 NC NC 10 11 12 13 14 15 16 17 18 19 20 21
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC CS NC NC ADR READY RESET NC NC VSS TCLK TENA RCLK CLSN TX NC NC
22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC DAL13 DAL14 DAL15 A16 A17 A22 A23 RX RENA NC A18 A19 NC NC A20 A21
Note: Pin 1 is marked for orientation.
17881B-2
2
Am79C90
NC
PRELIMINARY
TYPICAL ETHERNET/CHEAPERNET NODE
MAU TAP
DTE Ethernet Local CPU Local Memory Am79C90 C-LANCE Am7992B SIA
AUI Cable Am7996 Transceiver
Local Bus
Power Supply
Ethernet Coax DTE Cheapernet
Local CPU
Local Memory
Am79C90 C-LANCE
Am7992B SIA
Am7996 Transceiver RG58A/U or RG58C/U BNC "T"
Local Bus
Power Supply
Typical Ethernet 10BASE-T Node DTE AUI Cable MAU
Local CPU
Local Memory
Am79C90 C-LANCE
Am7992B SIA
Am79C98 Am79C100 Twisted-Pair Power Supply
Local Bus DTE
Local CPU
Local Memory
Am79C90 C-LANCE
Am7992B SIA
Am79C98 Am79C100 Twisted-Pair
Local Bus
17881C-4
AUI--Attachment Unit Interface
DTE--Data Terminal Equipment
MAU--Medium Attachment Unit
Am79C90
3
PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below.
AM79C90
P
C
B
OPTIONAL PROCESSING Blank = Standard Processing TR = Tape and Reel Packaging
OPERATING CONDITIONS C = Commercial (0°C to +70°C)
PACKAGE TYPE P = 48-Pin Plastic DIP (PD 048) J = 68-Pin Plastic Leaded Chip Carrier (PL 068)
SPEED Not Applicable DEVICE NUMBER/DESCRIPTION Am79C90 CMOS Local Area Network Controller for Ethernet
Valid Combinations AM79C90 PC, JC, JCTR
Valid Combinations Valid combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
Am79C90
PRELIMINARY
PIN DESCRIPTION A16A23
High Order Address Bus (Output, Three-State) Additional address bits to access a 24-bit address. These lines are driven as a Bus Master only.
Byte selection using Byte Mask is done as described by the following table:
BM1 LOW LOW HlGH HlGH BM0 LOW HIGH LOW HIGH Selection Whole Word Upper Byte Lower Byte None
ADR
Register Address Port Select (Input) When the C-LANCE is a Slave, ADR indicates which of the two register ports is selected. ADR LOW selects register data port; ADR HIGH selects register address por t. ADR must be valid throughout the data portion of the bus cycle and is only used by the C-LANCE when CS is LOW.
BYTE, BUSAKO--If CSR3 (00) BCON = 1 PIN 15 = BYTE (Output, Three-State) (48-Pin DlPs) PIN 16 = BUSAKO (Output) (48-Pin DIPs) Byte selection may also be done using the BYTE line and DAL00 line, latched during the address portion of the bus cycle. The C-LANCE drives BYTE only as a Bus Master and ignores it when a Bus Slave selection is done (similar to BM0, BM1). Byte selection is done as outlined in the following table:
BYTE LOW LOW HlGH HlGH DAL00 LOW HIGH LOW HIGH Selection Whole Word Illegal Condition Lower Byte Upper Byte
ALE/AS
Address Latch Enable (Output, Three-State) Used to demultiplex the DAL lines and define the address portion of the bus cycle. This l/O pin is programmable through bit (01) of CSR3. As ALE (CSR3 (01), ACON = 0), the signal transitions from a HIGH to a LOW during the address portion of the transfer and remains LOW during the data portion. ALE can be used by a Slave device to control a latch on the bus address lines. When ALE is HIGH, the latch is open, and when ALE goes LOW, the latch is closed. As AS (CSR3 (01), ACON = 1), the signal pulses LOW during the address portion of the bus transaction. The LOW-to-HlGH transition of AS can be used by a Slave device to strobe the address into a register. The C-LANCE drives the ALE/AS line only as a Bus Master.
BUSAKO is a bus request daisy chain output. If the chip i s not requesting the bus and it receives HLDA, BUSAKO will be driven LOW. If the C-LANCE is requesting the bus when it receives HLDA, BUSAKO will remain HIGH.
Byte Swapping
In order to be compatible with the variety of 16-bit microprocessors available to the designer, the C-LANCE may be programmed to swap the position of the upperand lower-order bytes on data involved in transfers with the internal FIFOs. Byte swapping is done when BSWP = 1. The most significant byte of the word in this case will appear on DAL lines 70 and the least significant byte on DAL lines 158. When BYTE = H (indicating a byte transfer) the table indicates on which part of the 16-bit data bus the actual data will appear. Whenever byte swap is activated, the only data that is swapped is data traveling to and from the Transmit/ Receive FIFOs.
BM0/BYTE, BM1/BUSAKO
(Output, Three-State) The two pins are programmable through bit (00) of CSR3. BM0, BM1--If CSR3 (00) BCON = 0 PIN 15 = BM0 (Output, Three-State) (48-Pin DlPs) PIN 16 = BM1 (Output, Three-State) (48-Pin DlPs) BM0, BM1 (Byte Mask). This indicates that the byte(s) on the DAL are to be read or written during this bus transaction. The C-LANCE drives these lines only as a Bus Master. It ignores the Byte Mask lines when it is a Bus Slave and assumes word transfers.
Am79C90
5
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