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Part: AMD-K6
Category:
Communication
-> Telephony
-> Voice Processors
Description: Amd-k6 Processor
Company: Advanced Micro Devices, Inc.
Datasheet: Download AMD-K6 datasheet File size : 689 kB
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Preliminary Information
AM D-K6
Processor
Data Sheet
®
Preliminary Information
© 1998 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in its products without notice in order to improve design or performance characteristics.
The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or systems without AMD's written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of AMD products, except as provided in AMD's Terms and Conditions of Sale for such products.
Trademarks AMD, the AMD logo, and combinations thereof, K86, AMD-K5, and the AMD-K6 logo are trademarks, and RISC86 and AMD-K6 are registered trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks, and Windows NT is a trademark of Microsoft Corporation. Netware is a registered trademark of Novell, Inc. MMX is a trademark and Pentium is a registered trademark of Intel Corporation. The TAP State Diagram is reprinted from IEEE Std 1149.1-1990 "IEEE Standard Test Access Port and Boundary-Scan Architecture," Copyright © 1990 by the Institute of Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. Information is reprinted with the permission of the IEEE. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Preliminary Information
20695H/0 -- March 1998
AMD-K6® Processor Data Sheet
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii About This Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part One
AM D-K6® Processor Family
1 2
3
AMD-K6® Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AMD-K6® Processor Microarchitecture Overview . . . . . . . . . 7 Enhanced RISC86® Microarchitecture . . . . . . . . . . . . . . . . . . . 8 Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . 11 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Branch History Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Branch Target Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4
2.5 2.6 2.7
3
Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point Register Data Types . . . . . . . . . . . . . . . . . . . . . 28 MMXTM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . . 37
Contents
iii
Preliminary Information AMD-K6® Processor Data Sheet
20695H/0 -- March 1998
3.2
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . 39 Task State Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Descriptors and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Instructions Supported by the AMD-K6 Processor . . . . . . . . 49
4 5
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 5.30 5.31 5.32 5.33 5.34 5.35 5.36 5.37 5.38 A20M# (Address Bit 20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 79 A[31:3] (Address Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ADS# (Address Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ADSC# (Address Strobe Copy) . . . . . . . . . . . . . . . . . . . . . . . . 81 AHOLD (Address Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 AP (Address Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 APCHK# (Address Parity Check) . . . . . . . . . . . . . . . . . . . . . . 84 BE[7:0]# (Byte Enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 BF[2:0] (Bus Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 BOFF# (Backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 BRDY# (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 BRDYC# (Burst Ready Copy) . . . . . . . . . . . . . . . . . . . . . . . . . 89 BREQ (Bus Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 CACHE# (Cacheable Access) . . . . . . . . . . . . . . . . . . . . . . . . . 90 CLK (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 D/C# (Data/Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 D[63:0] (Data Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DP[7:0] (Data Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 EADS# (External Address Strobe) . . . . . . . . . . . . . . . . . . . . . 94 EWBE# (External Write Buffer Empty) . . . . . . . . . . . . . . . . . 95 FERR# (Floating-Point Error) . . . . . . . . . . . . . . . . . . . . . . . . 96 FLUSH# (Cache Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 HIT# (Inquire Cycle Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 HITM# (Inquire Cycle Hit To Modified Line) . . . . . . . . . . . . 98 HLDA (Hold Acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . . 99 HOLD (Bus Hold Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . 100 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 INTR (Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 INV (Invalidation Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 KEN# (Cache Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LOCK# (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 M/IO# (Memory or I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 NA# (Next Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . 106 PCD (Page Cache Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 107 PCHK# (Parity Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
iv
Contents
Preliminary Information
20695H/0 -- March 1998
AMD-K6® Processor Data Sheet
5.39 5.40 5.41 5.42 5.43 5.44 5.45 5.46 5.47 5.48 5.49 5.50 5.51 5.52
RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 RSVD (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . 111 SMIACT# (System Management Interrupt Active) . . . . . . 112 STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TRST# (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 VCC2DET (VCC2 Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 W/R# (Write/Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 WB/WT# (Writeback or Writethrough) . . . . . . . . . . . . . . . . 116
6
Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1 6.2 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 123 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Data-NA# Requested. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Pipeline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Pipeline Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Memory Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Single-Transfer Memory Read and Write . . . . . . . . . . . . . . . 126 Misaligned Single-Transfer Memory Read and Write . . . . . 128 Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . 130 Burst Writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Misaligned I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . 135 Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 136 Hold and Hold Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . 136 HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 140 AHOLD-Initiated Inquire Miss. . . . . . . . . . . . . . . . . . . . . . . . 142 AHOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . 146 AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Bus Backoff (BOFF#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Locked Operation with BOFF# Intervention . . . . . . . . . . . . 154 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3
6.4
6.5
Contents
v
Others parts begin by am
AM-1 AM-2 AM-3 AM-4 AM-5 AM-6 AM-7 AM-8 AM-9 AM-10 AM-11 AM-12 AM-13 AM-14 AM-15 AM-16 AM-17 AM-18 AM-19 AM-20 AM-21 AM-22 AM-23 AM-24 AM-25 AM-26 AM-27 AM-28 AM-29 AM-30 AM-31 AM-32 AM-33 AM-34 AM-35 AM-36 AM-37 AM-38 AM-39 AM-40 AM-41 AM-42 AM-43 AM-44 AM-45 AM-46 AM-47 AM-48 AM-49 AM-50 AM-51 AM-52 AM-53 AM-54 AM-55 AM-56 AM-57 AM-58 AM-59 AM-60 AM-61 AM-62 AM-63 AM-64 AM-65 AM-66 AM-67 AM-68 AM-69 AM-70 AM-71 AM-72 AM-73 AM-74 AM-75 AM-76 AM-77 AM-78 AM-79 AM-80 AM-81 AM-82 AM-83 AM-84 AM-85 AM-86 AM-87 AM-88 AM-89 AM-90 AM-91 AM-92 AM-93 AM-94 AM-95 AM-96 AM-97 AM-98 AM-99 AM-100 AM-101 AM-102 AM-103 AM-104 AM-105
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