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Details, datasheet, quote on part number:PALCE16V8Q-5JC5
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Datasheet text preview:
FINAL
COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25
PALCE16V8 Family
EE CMOS 20-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s Pin and function compatible with all 20-pin GAL devices s Electrically erasable CMOS technology provides reconfigurable logic and full testability s High-speed CMOS technology -- 5-ns propagation delay for "-5" version -- 7.5-ns propagation delay for "-7" version s Direct plug-in replacement for the PAL16R8 series and most of the PAL10H8 series s Outputs programmable as registered or combinatorial in any combination s Peripheral Component Interconnect (PCI) compliant s Programmable output polarity s Programmable enable/disable control s Preloadable output registers for testability s Automatic register reset on power up s Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages s Extensive third-party software and programmer support through FusionPLD partners s Fully tested for 100% programming and functional yields and high reliability s 5 ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8 and PAL10H8 series devices, with the exception of the PAL16C1. The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an activehigh or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell. AMD's FusionPLD program allows PALCE16V8 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program also greatly reduces design time since a designer can use a tool that is already installed and familiar.
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Publication# 16493 Rev. D Issue Date: February 1996
Amendment /0
AMD
BLOCK DIAGRAM
I1 I8 CLK/I0
8
Programmable AND Array 32 x 64
MACRO MC0
MACRO MC1
MACRO MC2
MACRO MC3
MACRO MC4
MACRO MC5
MACRO MC6
MACRO MC7
OE/I9
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7 16493D-1
CONNECTION DIAGRAMS Top View DIP/SOIC
CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2
I5 2 C
PLCC/LCC
V LK/I0 I CC I/O7
3 I I3
I4
I1
1
20 19
1 18 17 16 15
I/O6 I/O5 I/O4 I/O3 I /O2
4 5 6 7 8 9 2
O
I/O1 I/O0 OE/I9
I6 7
4
16493D-2
10 11 12 13
IE/I9
NI D
PIN DESIGNATIONS
CLK GND I I/O OE VCC = = = = = = Clock Ground Input Input/Output Output Enable Supply Voltage PALCE16V8 Family
1
G/O1
I/O0
Note: Pin 1 is marked for orientation.
8
6493D-3
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AMD
ORDERING INFORMATION Commercial and Industrial Products
AMD programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE 16 V 8 H -5 P C /5
FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable NUMBER OF ARRAY INPUTS OUTPUT TYPE V = Versatile NUMBER OF OUTPUTS POWER H = Half Power (90 125 mA ICC) Q = Quarter Power (55 mA ICC) SPEED -5 = 5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD -25 = 25 ns tPD
OPTIONAL PROCESSING Blank = Standard Processing PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 = Second Revision (Same Algorithm as /4)
OPERATING CONDITIONS C = Commercial (0°C to +75°C) I = Industrial (40°C to +85°C) PACKAGE TYPE P = 20-Pin Plastic DIP (PD 020) J = 20-Pin Plastic Leaded Chip Carrier (PL 020) S = 20-Pin Plastic Gull-Wing Small Outline Package (SO 020)
Valid Combinations PALCE16V8H-5 PALCE16V8H-7 PALCE16V8H-10 PALCE16V8Q-10 PALCE16V8H-15 PALCE16V8Q-15 PALCE16V8Q-20 PALCE16V8H-25 PALCE16V8Q-25 JC PC, JC PC, JC, SC, PI, JI PC, JC, SC PC, JC, SC, PI, JI PC, JC PI, JI PC, JC, SC, PI, JI PC, JC, PI, JI /5 /4 /5
Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Blank, /4
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PALCE16V8H-5/7/10/15/25, Q-10/15/25 (Com'l) H-10/15/25, Q-20/25 (Ind)
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