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Details, datasheet, quote on part number:PALCE20V8Q-20JC
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Datasheet text preview:
FINAL
COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s Pin and function compatible with all GAL s s
Advanced Micro Devices
s Peripheral Component Interconnect (PCI)
s s s
20V8/As Electrically erasable CMOS technology provides reconfigurable logic and full testability High-speed CMOS technology -- 5-ns propagation delay for "-5" version -- 7.5-ns propagation delay for "-7" version Direct plug-in replacement for a wide range of 24-pin PAL devices Programmable enable/disable control Outputs individually programmable as registered or combinatorial
compliant
s Preloadable output registers for testability s Automatic register reset on power-up s Cost-effective 24-pin plastic SKINNYDIP and
28-pin PLCC packages
s Extensive third-party software and programmer
support through FusionPLD partners
s Fully tested for 100% programming and func-
tional yields and high reliability
s Programmable output polarity s 5-ns version utilizes a split leadframe for
improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices. Device logic is automatically configured according to the user's design specification. A design is implemented using any of a number of popular design software packages, allowing automatic creation of a programming file based on Boolean or state equations. Design software also verifies the design and can provide test vectors for the finished device. Programming can be accomplished on standard PAL device programmers. The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.
BLOCK DIAGRAM
10
I1 I10
CLK/I0
Programmable AND Array 40 x 64
Input Mux.
MACRO MC0
MACRO MC1
MACRO MC2
MACRO MC3
MACRO MC4
MACRO MC5
MACRO MC6
MACRO MC7
Input Mux.
OE/I11 I12
Publication# 16491 Rev. D Issue Date: February 1996
I/O0
I/O1
I/O2
I/O4
I/O4
I/O5
I/O6
I/O7
I13
16491D-1
Amendment /0
2-155
AMD
CONNECTION DIAGRAMS (Top View) SKINNYDIP
CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I13 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I12 OE/I11
16491D-2
PLCC/LCC
CLK/I0 NC VCC I/O7 25 24 23 22 21 20 19 12 13 14 15 16 17 18 GND NC OE/I11 I12 I/O0
16491D-3
4 I3 I4 I5 NC I6 I7 I8 5 6 7 8 9 10 11
3 2 1 28 27 26 I/O6 I/O5 I/O4 NC I/O3 I/O2 I/O1
Note: Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK GND I I/O NC OE VCC = Clock = Ground = Input = Input/Output = No Connect = Output Enable = Supply Voltage
2-156
PALCE20V8 Family
I9 I10
I13
I2 I1
AMD
ORDERING INFORMATION Commercial and Industrial Products
AMD programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
PAL FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable NUMBER OF ARRAY INPUTS OUTPUT TYPE V = Versatile NUMBER OF FLIP-FLOPS POWER H = Half Power (90-125 mA ICC) Q = Quarter Power (55 mA ICC) SPEED -5 = 5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD -25 = 25 ns tPD
CE
20 V 8 H -5 P C /5
PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 Second Revision (Same algorithm as /4) OPERATING CONDITIONS C = Commercial (0°C to +75°C) I = Industrial (40°C to +85°C)
PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028)
Valid Combinations PALCE20V8H-5 JC /5 PALCE20V8H-7 Blank, /4 PALCE20V8H-10 PC, JC /5 PALCE20V8Q-10 PALCE20V8H-15 PC, JC, PI, JI PALCE20V8Q-15 PC, JC Blank, /4 PALCE20V8Q-20 PI, JI PALCE20V8H-25 PC, JC, PI, JI PALCE20V8Q-25
Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
PALCE20V8H-5/7/10/15/25, Q-10/15/25 (Com'l) PALCE20V8H-15/25, Q-20/25 (Ind)
2-157
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