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Part: S29WS256N0LBFW010
Category:
Memory
-> Flash
-> 256 Mb
Description: CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory<<<>>>the WSXXXN Family Consists of 256, 128, And 64 Mbit, 1.8 Volt-only, Simultaneous<<<>>>Read/Write, Burst Mode Flash Memory Devices, Organized as 16, 8, or 4 Mwords<<<>>>of 16 Bits. These Devices Use a Single VCC of 1.70 to 1.95 V to Read, Program, And<<<>>>erase The Memory Array. A 9.0-volt VHH on Acc May be Used For Faster Program<<<>>>performance in a Factory Setting. These Devices CAN be Programmed in Standard<<<>>>ePROM Programmers.<<<>>>at 80 MHZ And 1.8V Vio, The Device Provides a Burst Access of 9 NS at 30 PF With an Initial Latency of 69 NS at 30 PF. At 66 MHZ And 1.8V Vio, The Device Provides a Burst Access of 11.2 NS at 30 PF With an Initial Latency of 69 NS at 30 PF. At 54 MHZ And 1.8V Vio, The Device Provides a Burst Access of 13.5 NS at 30 PF With an Initial Latency of 69 NS at 30 PF. The Device Operates Within The Industrial Temperature<<<>>>range of -40 C to +85 C or Wireless Temperature Range of -25 C to +85 C. These Devices Are Offered in MCP Compatible Fbga Packages. See The Product Selector Guide For Detailsthe Simultaneous Read/write Architecture Provides Simultaneous Operationby Dividing The Memory Space Into Sixteen Banks. The Device CAN Improve Overall<<<>>>system Performance BY Allowing a Host System to Program or Erase in One Bank, Then Immediately And Simultaneously Read From Another Bank, With Zero Latency. This Releases The System From Waiting For The Completion of Program or Erase Operations.<<<>>><<<>>>single 1.8 Volt Read, Program And Erase (1.70 To<<<>>>1.95 Volt)<<<>>> Manufactured on 110 NM Mirrorbittm Process<<<>>>technology<<<>>> Versatileio (VIO) Feature<<<>>> Device Generates Data Output Voltages And Tolerates Data Input Voltages as Determined BY The Voltage on The Vio Pin<<<>>> Vio Options Available For 1.8 V (1.70 V 1.95 V)<<<>>> Simultaneous Read/write Operation<<<>>> Data CAN be Continuously Read From One Bank While Executing Erase/program Functions in Another Bank Zero Latency Between Read And Write Operations<<<>>> Sixteen Bank Architecture: Each Bank Consists Of<<<>>>16Mb (WS256N) / 8Mb (WS128N) / 4Mb (WS064N)<<<>>> Programable Burst Interface<<<>>> 2 Modes of Burst Read Operation Linear Burst: 32, 16, And 8 Words With or Without Wrap-around<<<>>> Continuous Sequential Burst<<<>>> Secsitm (Secured Silicon) Sector Region<<<>>> 256 Words Accessible Through a Command Sequence, 128 Words For The Factory Secsi Sector And 128 Words For The Customer Secsi Sector.<<<>>> Non-erasable Region<<<>>> Sector Architecture<<<>>> S29WS256N: Eight 16 Kword Sectors And Two-hundred-fifty-four 64 Kword Sectors S29WS128N: Eight 16 Kword Sectors And One-hundred-twenty-six 64 Kword Sectors S29WS064N: Eight 16 Kword Sectors And Sixty-two 64 Kword Sectors Banks 0 And 15 Each Contain 16 Kword Sectors And 64 Kword Sectors; Other Banks Each Contain 64 Kword Sectors<<<>>> Eight 16 Kword Boot Sectors, Four at The Top of The<<<>>>address Range, And Four at The Bottom of The Address<<<>>>range
Company: Advanced Micro Devices, Inc.
Datasheet: Download S29WS256N0LBFW010 datasheet File size : 1958 kB
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Datasheet text preview:
S29WSxxxN MirrorBitTM Flash Family
S29WS256N, S29WS128N, S29WS064N 256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
PRELIMINARY
Distinctive Characteristics
Architectural Advantages
Single 1.8 volt read, program and erase (1.70 to 1.95 volt) Manufactured on 110 nm MirrorBitTM process technology VersatileIOTM (VIO) Feature -- Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin -- VIO options available for 1.8 V (1.70 V 1.95 V) Simultaneous Read/Write operation -- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency between read and write operations -- Sixteen bank architecture: Each bank consists of 16Mb (WS256N) / 8Mb (WS128N) / 4Mb (WS064N) Programable Burst Interface -- 2 Modes of Burst Read Operation -- Linear Burst: 32, 16, and 8 words with or without wrap-around -- Continuous Sequential Burst SecSiTM (Secured Silicon) Sector region -- 256 words accessible through a command sequence, 128 words for the Factory SecSi Sector and 128 words for the Customer SecSi Sector. -- Non-erasable region Sector Architecture -- S29WS256N: Eight 16 Kword sectors and twohundred-fifty-four 64 Kword sectors -- S29WS128N: Eight 16 Kword sectors and onehundred-twenty-six 64 Kword sectors -- S29WS064N: Eight 16 Kword sectors and sixty-two 64 Kword sectors -- Banks 0 and 15 each contain 16 Kword sectors and 64 Kword sectors; Other banks each contain 64 Kword sectors -- Eight 16 Kword boot sectors, four at the top of the address range, and four at the bottom of the address range Cycling Endurance: 100,000 cycles per sector typical Data Retention: 20 years typical MCP-Compatible Packages -- 84-ball (8 mm x 11.6 mm) FBGA package for WS256N -- 84-ball (8 mm x 11.6 mm) FBGA package for WS128N -- 80-ball (7 mm x 9 mm) FBGA package for WS064N
Performance Characteristics
Read access times at 80/66/54 MHz -- Burst access times of 9/11.2/13.5 ns -- Synchronous initial latency of 69/69/69 ns -- Asynchronous random access times of 70/70/70 ns Program and Erase Performance -- Typical word programming time of 40 µs -- Typical effective word programming time of 9.4 µs utilizing a 32-Word Write Buffer at VCC Level -- Typical effective word programming time of 6 µs utilizing a 32-Word Write Buffer at ACC Level -- Typical sector erase time of 150 ms for 16 Kword sectors and 800 ms sector erase time for 64 Kword sectors Power dissipation (typical values @ 66 MHz) -- Continuous Burst Mode Read: 35 mA -- Simultaneous Operation: 50 mA -- Program: 19 mA -- Erase: 19 mA -- Standby mode: 20 µA
Hardware Features
Sector Protection -- Write protect (WP#) function allows protection of eight outermost boot sectors, four at top and four at bottom of memory, regardless of sector protect status Handshaking feature available -- Provides host system with minimum possible latency by monitoring RDY Boot Option -- Dual Boot Low VCC write inhibit
Security Features
Advanced Sector Protection consists of the two following modes of operation Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level
Publication Number S29WSxxxN_00
Revision C
Amendment 0
Issue Date June 14, 2004
Preliminary
Password Sector Protection -- A sophisticated sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector using a user-defined 64-bit password
Program Suspend/Resume -- Suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences
Software Features
Supports Common Flash Memory Interface (CFI) Software command set compatible with JEDEC 42.4 standards Data# Polling and toggle bits -- Provides a software method of detecting program and erase operation completion Erase Suspend/Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
Additional Features
Program Operation -- Ability to perform synchronous and asynchronous program operation independent of burst control register setting ACC input -- Acceleration function reduces programming and erase time in a factory setting.
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S29WSxxxN MirrorBitTM Flash Family
S29WSxxxN_00C0 June 14, 2004
Preliminary
General Description
The WSxxxN family consists of 256, 128, and 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory devices, organized as 16, 8, or 4 Mwords of 16 bits. These devices use a single VCC of 1.70 to 1.95 V to read, program, and erase the memory array. A 9.0-volt VHH on ACC may be used for faster program performance in a factory setting. These devices can be programmed in standard EPROM programmers. At 80 MHz and 1.8V VIO, the device provides a burst access of 9 ns at 30 pF with an initial latency of 69 ns at 30 pF. At 66 MHz and 1.8V VIO, the device provides a burst access of 11.2 ns at 30 pF with an initial latency of 69 ns at 30 pF. At 54 MHz and 1.8V VIO, the device provides a burst access of 13.5 ns at 30 pF with an initial latency of 69 ns at 30 pF. The device operates within the industrial temperature range of -40°C to +85°C or wireless temperature range of -25°C to +85°C. These devices are offered in MCP compatible FBGA packages. See the product selector guide for details The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into sixteen banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The devices are divided into banks and sectors as shown in the following table: Bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Quantity of Sectors (WS256N/WS128N/WS064N) 4/4/4 15/7/3 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 15/7/3 4/4/4 Sector Size 16 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 16 Kwords
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin.
June 14, 2004 S29WSxxxN_00C0
S29WSxxxN MirrorBitTM Flash Family
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