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Part: AM28F010A-90
Category:
Memory
-> Flash
-> Parallel Flash
-> 1M
Description: Flash 12v 10k Cycle Embedded Algorithm Only: 128kx8
Company: Advanced Micro Systems, Inc.
Datasheet: Download AM28F010A-90 datasheet File size : 427 kB
Request For quote: Find where to buy AM28F010A-90
Datasheet text preview:
FINAL
Am28F010A
1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
s High performance -- Access times as fast as 70 ns s CMOS low power consumption -- 30 mA maximum active current -- 100 µA maximum standby current -- No data retention power consumption s Compatible with JEDEC-standard byte-wide 32-pin EPROM pinouts -- 32-pin PDIP -- 32-pin PLCC -- 32-pin TSOP s 100,000 write/erase cycles minimum s Write and erase voltage 12.0 V ±5% s Latch-up protected to 100 mA from 1 V to VCC +1 V s Embedded Erase Electrical Bulk Chip Erase -- 5 seconds typical chip erase, including pre-programming s Embedded Program -- 14 µs typical byte program, including time-out -- 4 seconds typical chip program s Command register architecture for microprocessor/microcontroller compatible write interface s On-chip address and data latches s Advanced CMOS flash memory technology -- Low cost single transistor memory cell s Embedded algorithms for completely self-timed write/erase operations
GENERAL DESCRIPTION
The Am28F010A is a 1 Megabit Flash memory organized as 128 Kbytes of 8 bits each. AMD's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The Am28F010A is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F010A is erased when shipped from the factory. The standard Am28F010A offers access times of as fast a s 70 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#) and output enable (OE#) controls. AMD's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F010A uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels d u r i n g erase and programming, while maintaining maximum EPROM compatibility. T h e A m 2 8 F 0 1 0 A i s com p a t i b l e w i t h th e A M D A m 2 8 F 2 5 6 A , Am28F512A, and Am28F020A Flash memories. All devices in the Am28Fxxx family follow the JEDEC 32-pin pinout standard. In addition, all devices
Publication# 16778 Rev: D Amendment/+2 Issue Date: May 1998
within this family that offer Embedded Algorithms use the same command set. This offers designers the flexibility to retain the same device footprint and command set, at any density between 256 Kbits and 2 Mbits. AMD's Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The AMD cell is designed to optimize the erase and programm in g mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electr ic fields for erase and programming operations prod u c e s reliable cycling. The Am28F010A uses a 12.0±5% VPP input to perform the erase and programming functions. The highest degree of latch-up protection is achieved with AMD's proprietary non-epi process. Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1 V to VCC +1 V. AMD's Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of q u a l i t y, reliability, and cost effectiveness. The Am28F010A electrically erases all bits simultaneously u s i n g Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
Embedded Program
T h e Am28F010A is byte programmable using the Embedded Program algorithm, which does not require the system to time-out or verify the data programmed. The typical room temperature programming time of this device is two seconds.
Embedded Erase
The entire device is bulk erased using the Embedded E r a se algorithm, which automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internal to the device. Typical erasure time at room temperature is five seconds, including preprogramming.
Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms
Am28F010A with Embedded Algorithms Embedded Programming Algorithm vs. Flashrite Programming Algorithm AMD's Embedded Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, verifies the programming, and counts the number of sequences. A status bit, Data# Polling, provides the user with the programming operation status. Am28F010 using AMD Flashrite and Flasherase Algorithms The Flashrite Programming algorithm requires the user to write a program set-up command, a program command, (program data and address), and a program verify command, followed by a read and compare operation. The user is required to time the programming pulse width in order to issue the program verify command. An integrated stop timer prevents any possibility of overprogramming. Upon completion of this sequence, the data is read back from the device and compared by the user with the data intended to be written; if there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 25 times. The Flasherase Erase algorithm requires the device to be completely programmed prior to executing an erase command. To invoke the erase operation, the user writes an erase set-up command, an erase command, and an erase verify command. The user is required to time the erase pulse width in order to issue the erase verify command. An integrated stop timer prevents any possibility of overerasure. Upon completion of this sequence, the data is read back from the device and compared by the user with erased data. If there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 1,000 times.
Embedded Erase Algorithm vs. Flasherase Erase Algorithm
AMD's Embedded Erase algorithm requires the user to only write an erase setup command and erase command. The device automatically pre-programs and verifies the entire array. The device then automatically times the erase pulse width, verifies the erase operation, and counts the number of sequences. A status bit, Data# Polling, provides the user with the erase operation status.
Commands are written to the command register using standard microprocessor write timings. Register cont e n t s serve as input to an internal state-machine, which controls the erase and programming circuitry. Dur ing write cycles, the command register internally latches addresses and data needed for the programming and erase operations. For system design simplification, the Am28F010A is designed to support either WE# or CE# controlled writes. During a system write
c y c l e, addresses are latched on the falling edge of W E# or CE#, whichever occurs last. Data is latched on the rising edge of WE# or CE#, whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the r e s t of this text. All setup and hold times are with respect to the WE# signal.
2
Am 2 8 F 0 1 0 A
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (VCC = 5.0 V ± 10%) Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns) -70 70 70 35 -90 90 90 35 Am28F010A -120 120 120 50 -150 150 150 55 -200 200 200 55
BLOCK DIAGRAM
DQ0DQ7
V CC VSS VPP
Erase Voltage Switch Input/Output Buffers
To Array WE# State Control Command Register CE# OE# Program Voltage Switch
Chip Enable Output Enable Logic Data Latch
Embedded Algorithms Y-Decoder Address Latch Program/Erase Pulse Timer Y-Gating
Low VCC Detector
X-Decoder
1,048,576 Bit Cell Matrix
A0A16
16778D-1
Am28F010A
3
CONNECTION DIAGRAMS
PDIP VP P A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# (W#) PLCC
WE# (W#)
VCC
A12
A15
A16
VPP
NC A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7 DQ6 DQ5 DQ4 DQ3
4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
3
2
1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE (G) A10 CE# (E#) DQ7
14 15 16 17 18 19 20 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 VSS
16778D-2
NC
16778D-3
Note: Pin 1 is marked for orientation.
4
Am 2 8 F 0 1 0 A
CONNECTION DIAGRAMS (continued)
A11 A9 A8 A13 A14 NC WE# VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin TSOP--Standard Pinout
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin TSOP--Reverse Pinout
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 NC WE# VCC VPP A16 A15 A12 A7 A6 A5 A4
16778D-4
LOGIC SYMBOL
17 A0A16 DQ0DQ7 CE# (E#) OE# (G#) WE# (W#) 8
16778D-5
Am28F010A
5
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