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Part: AM79C100
Category:
Communication
-> Network
-> Ethernet/DS1/E1 (T1/E1)
-> Transceivers
-> Transceiver/Repeater
Description: Pcnet(tm)-fast i i i Single-chip 10/100 MBPS Pci Ethernet Controller With Integrated PHY
Company: Advanced Micro Systems, Inc.
Datasheet: Download AM79C100 datasheet File size : 1108 kB
Request For quote: Find where to buy AM79C100
Datasheet text preview:
FINAL
Am79C100
Twisted-Pair Ethernet Transceiver Plus (TPEX Plus)
DISTINCTIVE CHARACTERISTICS
s CMOS device provides IEEE 802.3-compliant operation and low operating current from a single +5 V supply s Power Down mode for reduced power consumption in battery-powered applications s Automatic twisted-pair link integrity s Pin-selectable twisted-pair receive polarity detection and automatic inversion of the receive signal. Polarity indication output pin can directly drive an LED. s Pin-selectable twisted-pair link integrity test capability conforming to the IEEE 802.3 standard. Link status pin can directly drive an LED. s Transmit, receive, and collision status indications available on separate, dedicated pins s Outputs can directly drive LEDs with pulses stretched to ensure LED visibility s Internal twisted-pair transmitter digital predistortion circuit to reduce medium-induced jitter s Pin-selectable SQE Test (heartbeat) enable s AUI loopback, Jabber Control, and SQE Test functions comply with the 10BASE-T standard s User-selectable loopback operations s Pin-selectable twisted-pair receive threshold programming for extended distance line lengths
GENERAL DESCRIPTION
The Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX Plus) is an integrated circuit that implements the m e d i u m attachment unit (MAU) functions for the twisted-pair medium, as specified by the supplement to the IEEE 802.3 standard (Type 10BASE-T). This device provides the necessary electrical and functional interface between the IEEE 802.3 standard attachment unit interface (AUI) and the twisted-pair cable. A network based on the 10BASE-T standard can use unshielded twisted-pair cables, providing an economical solution to networking by allowing the use of existing telephone wiring. The Am79C100 provides a minimal component count and a cost-effective solution to the d e s i g n and implementation of 10BASE-T standard networks. TPEX Plus provides twisted-pair driver and receiver circuits, including on-board transmit digital predistortion, receiver squelch, and an AUI port with pin-selectable SQE Test enable. The device provides a number of additional features, including Link Status indication with a u t o m a t i c twisted-pair receive polarity detection/ c o r r e c t i o n and indication; pin-selectable receive t h r e s h o l d programming for extended distance line lengths; and Receive Carrier Sense, Transmit Active and Collision Present indications. The device provides s e p a ra t e twisted-pair Link Status, Polarity Status, Receive, Transmit, and Collision outputs to drive LEDs directly.
Publication# 16511 Rev: B Amendment/0 Issue Date: May 1994
1
AMD
BLOCK DIAGRAM
TEST1 TEST2 XMT COL RCV RXPOL LNKST
LED Driver Logic DO+ DO Line Receiver and Squelch Circuit Line Driver P and redistortion TXD+ TXD TXP+ TXP
Cabber J ontrol
CI+ CI SQE TEST DI+ DI PRDN/RST REXT U ttachment A nit Interface (AUI)
ine Driver L
Collision and L oopback C ontrol
Link Test State Machine
Line Driver
D Polarity etection and Auto Correction CVoltage O ntrolled o scillator
Line Receiver S and mart Squelch
RXD+ RXD LRT
Twisted-Pair I nterface
16511B-1
RELATED AMD PRODUCTS
Part No. Am7996 Am79C90 Am79C900 Am79C940 Am79C960 Am79C961 Am79C965 Am79C970 Am79C974 Am79C98 Am79C981 Am79C987 Description IEEE-802.3/Ethernet/Cheapernet Tap Transceiver CMOS Local Area Network Controller for EthernetTM (C-LANCE) Integrated Local Area Communications ControllerTM (ILACCTM) Media Access Controller for Ethernet (MACETM) PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) PCnet-ISA Single-Chip Ethernet Controller (with Microsoft® Plug n' Play support) PCnet-32 Single-Chip Ethernet Controller (for 386DX, 486 and VL buses) PCnet-PCI Single-Chip Ethernet Controller (for PCI bus) PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems Twisted-Pair Ethernet Transceiver (TPEX) Integrated Multiport Repeater PlusTM (IMR+TM) Hardware Implemented Management Information BaseTM (HIMIBTM)
2
Am79C100
CONNECTION DIAGRAM
PLCC
TXD+ TXD TXP+ DI+ CI+ DI CI 2
4 DVSS DVSS XMT LNKST COL AVSS DO+ 5 6 7 8 9 10 11
3
1 28 27 26 25 24 23 22 21 20 19 TXP DVDD TEST2 TEST1 SQE TEST LRT AVDD
12 13 14 15 16 17 18 RXPOL RXD DO REXT PRDN/RST RXD+ RCV
16511B-2
LOGIC SYMBOL
DVDD DO+ DO Attachment Unit Interface (AUI) DI+ DI CI+ CI SQE TEST TEST1 TEST2 REXT PRDN/RST DVSS
AVDD TXD+ TXP+ TXD TXP Am79C100 RXD+ RXD LRT RXPOL LNKST XMT RCV COL AVSS Twisted-Pair Interface
16511B-3
Am79C100
3
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below.
AM79C100
J
C
OPTIONAL PROCESSING Blank = Standard Processing
OPERATING CONDITIONS C = Commercial (0°C to +70°C)
PACKAGE TYPE J = 28-Pin Plastic Leaded Chip Carrier (PL 028)
SPEED Not Applicable DEVICE NUMBER/DESCRIPTION Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX Plus)
Valid Combinations AM79C100 JC
Valid Combinations Valid combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
Am79C100
PIN DESCRIPTION AVDD
Analog Power This pin supplies +5 V to analog portions of the TPEX Plus circuitry.
LNKST
Link Status Input/Output, Open Drain When this pin is tied LOW, the internal Link Test Receive function is disabled, and the Transmit and Receive functions will remain active regardless of arriving idle link pulses and data. TPEX Plus continues to generate idle link pulses irrespective of the status of this pin. As an output, this pin is driven LOW if the link is identified as functional. However, if the link is determined to be nonfunctional due to missing idle link pulses or data packets, then this pin is not driven (internally pulled HIGH). In the LOW output state, the pin is capable of sinking a maximum of 12 mA and can be used to drive an LED. In the absence of an external drive, the pin is internally pulled HIGH when inactive.
AVSS
Analog Ground This pin is the ground reference for analog portions of TPEX Plus circuitry.
CI+, CI
Control In Output AUI port differential driver.
COL
Collision Output, Open Drain This pin is driven LOW while the TPEX Plus is simultaneously receiving data on the AUI DO pins and the twisted-pair RXD pins, indicating that a collision condition exists. It is also driven if TPEX Plus enters the jabber condition due to excessive length of activity on the DO pair. In this case TPEX Plus will wait for a period of inactivity on DO for the "unjab" time of 250 to 750 ms, before the 10 MHz pattern on the CI pair is removed and COL returns inactive. COL will not be driven during SQE Test activity on the AUI CI pair. In the LOW output state, the pin is capable of sinking a maximum of 12 mA and can be used to drive an LED. The COL output is pulse stretched for 20 to 62 ms after the end of collision, to ensure LED visibility.
LRT
Low Receive Threshold Input, Active LOW When this pin is tied LOW, the internal twisted-pair receive thresholds are reduced by 4.5 dB from their original values (approximately 3/5 of the normal 10BASE-T val ue). With LRT in the HIGH state, the unsquelch threshold for the RXD± circuit will be 300 mV to 520 mV p e a k . With LRT in the LOW state, the unsquelch threshold for the RXD± circuit will be 180 mV to 312 mV peak. In either case, the RXD± circuit post unsquelch threshold will be approximately one-half of the initial unsquelch threshold.
PRDN/RST
Power Down/Reset Input, Active LOW Driving this input LOW resets the internal logic of TPEX Plus and places the device in a special Power Down mode. In the Power Down/Reset mode, all output drivers are placed in their inactive state.
DI+, DI
Data In Output AUI port differential driver.
DO+, DO
Data Out Input AUI port differential receiver.
REXT
External Resistor Input An external precision resistor is connected between this pin and AVDD in order to provide a current refere n c e for the internal voltage-controlled oscillator (VCO).
DVDD
Digital Power This pin supplies +5 V to digital portions of the TPEX Plus circuitry, including all transmit drivers.
RCV
Receive Output, Open Drain This pin is driven LOW while TPEX Plus is receiving data on the twisted-pair RXD pins and is transferring the received signal onto the AUI DI pair. The output is LOW during collision simultaneously with the COL pin.
DVSS
Digital Ground Two pins provide the ground reference for digital port i o n s of TPEX Plus circuitry, including all transmit drivers and the status indication LED drivers.
Am79C100
5
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