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Part: AM79C850
Category:
Communication
-> Network
-> FDDI
Description: Supernet 3
Company: Advanced Micro Systems, Inc.
Datasheet: Download AM79C850 datasheet File size : 1108 kB
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Datasheet text preview:
D
PRELIMINARY
Am79C850
SUPERNET® 3
ISTINCTIVE CHARACTERISTICS
s Compliant with the ANSI X3T9.5/ISO 9314
Advanced Micro Devices
s ANSI-compliant TP-PMD Stream Cipher
specification -- 100 Mbps data rate -- Timed token-passing protocol -- Ring topology s Complete memory management -- Supports 256K bytes of local frame buffer memory -- Supports buffer memory bandwidths of 200 Mbps and 400 Mbps -- Tag-Mode: minimum latency/highest performance buffer memory management, ideal for adapter card designs
Scrambling/Descrambling
s Full duplex operation: 200 Mbps continuous
data rate
s Supports both fiber optic and copper twisted-
pair media
s Diagnostic features
-- Built in Self Test (BIST) in Address Filter, Physical Layer Controller with Scrambler s Hardware Physical Connection Management support
s Low power consumption--reduction of more
than 25% from SUPERNET 2 solution
FUNCTIONAL OVERVIEW
SUPERNET 3 is a 208-pin CMOS integration of FDDI MAC, PHY, Address Filter, and clock generation and recovery functions. It is the third generation FDDI offering from AMD which integrates the SUPERNET 2 family of chips into a single-chip solution. Refer to the SUPERNET 2 data book (PID 15502C) for basic feature descriptions. The SUPERNET 3 is backward compatible to the SUPERNET 2 Tag Mode of operation in which the SUPERNET 3 buffer memory interface logic maintains the buffer memory as multiple FIFOs. The SUPERNET 3 provides DMA channels, arbitrates access to the network buffer memory, and controls the data path between the buffer memory and the medium. The MAC also implements the timed-token protocol and receive/transmit control as specified for the Media Access Control (MAC) sublayer of the ISO standard 9314-2 for FDDI. The Physical Layer functions defined by the ISO 9314-1 are performed by the SUPERNET 3. SUPERNET 3 implements on-chip digital clock recovery and transmit functions for fiber. To support copper media, the PHY-PMD interface is maintained and an external module can be implemented in the same footprint as the fiber optic transceiver to perform the MLT-3 encoding/decoding and equalization. SUPERNET 3 integrates the scrambler and descrambler functions for transmissions over copper media.
SUPERNET 3 FEATURES UPDATE
The basic feature description for SUPERNET 3 is provided in the SUPERNET 2 data book. The enhanced features are as listed below:
s This is a CMOS integration of the redesigned
FORMAC Plus, an enhanced PLC, a 32-entry address filter (AF, which is based on a Content Addressable Memory, or CAM, core), and a CMOS PDX core for clock and data recovery.
s A 32-entry, extensible and fully maskable AF
allows additional individual and group addresses to be supported.
s The physical data transmitter and receiver (PDX)
circuits are also embedded on-chip using proprietary digital clock-recovery technology.
s For the purposes of implementing copper PMD,
the scrambler/descrambler functions are embedded within the chip.
s The Buffer Memory interface has been modified to
support slower SRAM's (35 ns) without affecting backward compatibility with SUPERNET 2.
s SUPERNET 3 supports the FDDI single
attachment station (SAS) but is capable of supporting a dual attachment station (DAS)
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 19574 Rev. A Issue Date: April 1995
Amendment /0
AMD
PRELIMINARY
s All SUPERNET 3 registers will be initialized with a
configurations with an external physical layer controller.
s SUPERNET 3 has a Test Access Port and
default value on reset.
s The A, C indicator setting has been modified. It is
Boundary Scan Architecture, IEEE1149.1.
s SUPERNET 3 provides Built-in Self Test (BIST)
features for the Address Filter, and PLC-S.
s All registers are readable and writable by the Node
now possible to control the setting of the A, C indicators independent of the mode of operation (online, online special mode, and external loopback mode).
s Maskable `vectored-interrupts' are provided. It is
Processor. All reserved bits shall be read back as zero except where noted.
s The Receive Status (RS) pins are expanded from
5 to 6 pins to support enhanced status reporting.
s The Transmit Status (XS) pins are expanded from
now possible to detect the event causing the interrupt in the SUPERNET 3 in two cycles by reading the vector register which gives the vector of the status register followed by a read of the appropriate status register.
s An additional mode register (MDREG3) is
3 to 4 pins to support enhanced status reporting.
s Enhanced frame reception is possible by splitting
the receive queue.
s Modified TAG Mode of operation for easy
provided. Setting the bits in this mode register enables the additional SUPERNET 3 features.
conversion from NON-TAG SUPERNET 2 to SUPERNET 3.
2
SUPERNET 3
NPDATA NPADDR NPMODE 4 16 8 CS READY LSCLK BMCLK
BLOCK DIAGRAM
DS
R/W
MINTR
RST
X BCLK
Node Processor Interface Clock Logic
RBUS 10 10 3 TBUS 10 3 16 32 4 TX 10 RX
XPAR X
NPMEMREQ N PMHMACK E
DAS/SAS Control & Mux
8 2 8 2
HSREQ R SACK Q ATA1 D A TRL C
3
Enhanced F+
NPCONTROL
CU, XCL R CU, RCL R L PAR USR E LSB F BFERR EOTOFF T NCOFF RDAT 5
PRELIMINARY
TDI
TDO
TCK
TMS
XSAMAT
XDAMAT
RXAFCL RXAFCU
XSA_XACT
XDA_XACT
RXAFL[3:0]
RXAFU[3:0]
4
TRST
SUPERNET 3
2
NPDATA
6 16
NPADDR
Enhanced PLC S with D crambler escrambler
DDR B BD B DP DCAG T R SO D, WR F LXI R XS R S 6 4 8
X igital D 5 T R mitter/ eceiver ( DAT PDX)
LPBCK
TX+ RXRX+ S XSDI+ SDICRM
DATA2
RXINT 8 M CONTROL S ATCH TATUS 8 4
Address Filter
Tap Controller
4
AMD
3
AMD
PRELIMINARY
Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUPERNET 3 Features Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 3 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SUPERNET 2 Features not Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Miscellaneous Changes from SUPERNET 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Explanation of Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Slower Buffer Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 A, C Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Transmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Non-Tag Mode of Operation No Longer Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Modified TAG Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transmit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TDAT Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mode Register 3 (MDREG3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Receive Flush/Transmit Inhibit pin FLXI (input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Single Frame Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Receive Queue Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Address Bit Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Auto-Unlocking of Receive Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Symbol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Dual Attachment Station (DAS) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Changes and Enhancements to PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Summary of Changes to Status and Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Status Register 3 (ST3U & ST3L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Parity Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Node Processor Synchronous Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Address Filter (AF) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Function of the Address Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Node Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4
SUPERNET 3
PRELIMINARY
AMD
Table of Contents (continued)
Address Filter Test Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Test Logic Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Writing Entries into the AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Finding Entries in the AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Invalidating Entries in the AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PDX Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Default Timer and Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 SUPERNET 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SUPERNET 3 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SUPERNET 3 Command Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SUPERNET 3 Command Registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SUPERNET 3 Command Registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Revision I.D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DC CHARACTERISTICS over operating ranges unless otherwise specified . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 MAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 PQR208, Trimmed and Formed 208-Pin Plastic Quad Flat Pack (measured in inches) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SUPERNET 3
5
Others parts begin by am
AM-1 AM-2 AM-3 AM-4 AM-5 AM-6 AM-7 AM-8 AM-9 AM-10 AM-11 AM-12 AM-13 AM-14 AM-15 AM-16 AM-17 AM-18 AM-19 AM-20 AM-21 AM-22 AM-23 AM-24 AM-25 AM-26 AM-27 AM-28 AM-29 AM-30 AM-31 AM-32 AM-33 AM-34 AM-35 AM-36 AM-37 AM-38 AM-39 AM-40 AM-41 AM-42 AM-43 AM-44 AM-45 AM-46 AM-47 AM-48 AM-49 AM-50 AM-51 AM-52 AM-53 AM-54 AM-55 AM-56 AM-57 AM-58 AM-59 AM-60 AM-61 AM-62 AM-63 AM-64 AM-65 AM-66 AM-67 AM-68 AM-69 AM-70 AM-71 AM-72 AM-73 AM-74 AM-75 AM-76 AM-77 AM-78 AM-79 AM-80 AM-81 AM-82 AM-83 AM-84 AM-85 AM-86 AM-87 AM-88 AM-89 AM-90 AM-91 AM-92 AM-93 AM-94 AM-95 AM-96 AM-97 AM-98 AM-99 AM-100 AM-101 AM-102 AM-103 AM-104 AM-105
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