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Part: AMD-K6-2/266BNZ
Category:
Microprocessors
-> RISC
-> X86/i960(tm) Family
Description: Risc86(r) Processor With 3dnow(tm)
Company: Advanced Micro Systems, Inc.
Datasheet: Download AMD-K6-2/266BNZ datasheet File size : 689 kB
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Preliminary Information
®
Mobile
AM D-K6-2
®
Processor Data Sheet
Publication # 21896 Rev : E Issue Date: May 2000
Amendment/0
Preliminary Information
© 2000 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
Trademarks AMD, the AMD logo, K6, 3DNow!, and combinations thereof, and Super7 are trademarks, and AMD-K6 and RISC86 are registered trademarks of Advanced Micro Devices, Inc. MMX is a trademark of Intel Corporation. Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Preliminary Information
218 96E/0 -- May 2000
Mobile AMD-K6®-2 Processor Data Sheet
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi About This Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Part One
Mobile AMD-K6®-2 Processor
1
1
Mobile AMD-K6®-2 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Super7TM Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Super7 Platform Enhancements: . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Mobile AMD-K6®-2 Processor Microarchitecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Enhanced RISC86® Microarchitecture . . . . . . . . . . . . . . . . . . . 8 Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . 11 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Register X and Y Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Branch History Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Branch Target Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3
2.4
2.5 2.6 2.7
3 4 5
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Mobile AMD-K6-2 Processor Operation . . . . . . . . . . . . . . . . . 37
5.1 5.2 Process Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Contents
iii
Preliminary Information Mobile AMD-K6®-2 Processor Data Sheet
218 96E/0 -- May 2000
5.3
Stop Grant Inquire State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . 42 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SMM Operating Mode and Default Register Values . . . . . . . 42 SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O Trap Dword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . . . 51
6
Signal Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 53
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 53 Clock Switching Characteristics for 100-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Clock Switching Characteristics for 66-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . . 55 Output Delay Timings for 100-MHz Bus Operation . . . . . . . 56 Input Setup and Hold Timings for 100-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Output Delay Timings for 66-MHz Bus Operation . . . . . . . . 60 Input Setup and Hold Timings for 66-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . 64
7
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.1 7.2 7.3 7.4 7.5 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . . 77 Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 77
8
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . 79 Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 82
iv
Contents
Preliminary Information
218 96E/0 -- May 2000
Mobile AMD-K6®-2 Processor Data Sheet
9
Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.1 9.2 9.3 321-Pin Staggered CPGA Package Specification . . . . . . . . . 83 360-Pin Model 8 CBGA Package Specification . . . . . . . . . . . 85 360-Pin CBGA Mechanical Specification . . . . . . . . . . . . . . . . 87
10
Pin Description Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.1 10.2 10.3 360-Pin CBGA Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 89 321-Pin CPGA Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Pin Designations by Functional Grouping . . . . . . . . . . . . . . . 93
11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Part Two
Mobile AMD-K6-2-P Processor
12
97
Mobile AMD-K6-2-P Processor . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.1 Super7 Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Super7 Platform Enhancements: . . . . . . . . . . . . . . . . . . . . . . 101
13
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1 13.2 13.3 13.4 13.5 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . 110 Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . . . 111
14
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 113 Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115
15
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Contents
v
Others parts begin by am
AM-1 AM-2 AM-3 AM-4 AM-5 AM-6 AM-7 AM-8 AM-9 AM-10 AM-11 AM-12 AM-13 AM-14 AM-15 AM-16 AM-17 AM-18 AM-19 AM-20 AM-21 AM-22 AM-23 AM-24 AM-25 AM-26 AM-27 AM-28 AM-29 AM-30 AM-31 AM-32 AM-33 AM-34 AM-35 AM-36 AM-37 AM-38 AM-39 AM-40 AM-41 AM-42 AM-43 AM-44 AM-45 AM-46 AM-47 AM-48 AM-49 AM-50 AM-51 AM-52 AM-53 AM-54 AM-55 AM-56 AM-57 AM-58 AM-59 AM-60 AM-61 AM-62 AM-63 AM-64 AM-65 AM-66 AM-67 AM-68 AM-69 AM-70 AM-71 AM-72 AM-73 AM-74 AM-75 AM-76 AM-77 AM-78 AM-79 AM-80 AM-81 AM-82 AM-83 AM-84 AM-85 AM-86 AM-87 AM-88 AM-89 AM-90 AM-91 AM-92 AM-93 AM-94 AM-95 AM-96 AM-97 AM-98 AM-99 AM-100 AM-101 AM-102 AM-103 AM-104 AM-105
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