|
|
Part: AMD-K6-III
Category:
Microprocessors
-> RISC
-> X86/i960(tm) Family
Description: Processor
Company: Advanced Micro Systems, Inc.
Datasheet: Download AMD-K6-III datasheet File size : 689 kB
Request For quote: Find where to buy AMD-K6-III
Datasheet text preview:
AMD-K6-III
®
Processor Data Sheet
© 1999 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
Trademarks AMD, the AMD logo, K6, 3DNow!, and combinations thereof, K86, and Super7 are trademarks, and AMD-K6 and RISC86 are registered trademarks of Advanced Micro Devices, Inc. Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation. NetWare is a registered trademark of Novell, Inc. MMX is a trademark of Intel Corporation. The TAP State Diagram is reprinted from IEEE Std 1149.1-1990 "IEEE Standard Test Access Port and Boundary-Scan Architecture," Copyright © 1990 by the Institute of Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. Information is reprinted with the permission of the IEEE. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
21918B/0 -- October 1999
AMD-K6®-III Processor Data Sheet
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii 1 AMD-K6®-III Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Super7TM Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Super7TM Platform Enhancements. . . . . . . . . . . . . . . . . . . . . . . 3 Super7TM Platform Advantages . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 2.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AMD-K6®-III Processor Microarchitecture Overview . . . . . . 5 Enhanced RISC86® Microarchitecture . . . . . . . . . . . . . . . . . . . 6 Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . . 9 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 11 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register X and Y Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Branch History Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Branch Target Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
2.5 2.6 2.7
3
Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point Register Data Types . . . . . . . . . . . . . . . . . . . . . 28 MMXTM/3DNow!TM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MMXTM Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3DNow!TM Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Contents
iii
AMD-K6®-III Processor Data Sheet
21918B/0 -- October 1999
3.2
Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . . 37 Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . 45 Task State Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Descriptors and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Instructions Supported by the AMD-K6®-III Processor . . . . 54
4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A20M# (Address Bit 20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 85 A[31:3] (Address Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADS# (Address Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ADSC# (Address Strobe Copy) . . . . . . . . . . . . . . . . . . . . . . . . 87 AHOLD (Address Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 AP (Address Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 APCHK# (Address Parity Check) . . . . . . . . . . . . . . . . . . . . . . 90 BE[7:0]# (Byte Enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 BF[2:0] (Bus Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 BOFF# (Backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 BRDY# (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 BRDYC# (Burst Ready Copy) . . . . . . . . . . . . . . . . . . . . . . . . . 95 BREQ (Bus Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 CACHE# (Cacheable Access) . . . . . . . . . . . . . . . . . . . . . . . . . 96 CLK (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 D/C# (Data/Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 D[63:0] (Data Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DP[7:0] (Data Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 EADS# (External Address Strobe) . . . . . . . . . . . . . . . . . . . . 100 EWBE# (External Write Buffer Empty) . . . . . . . . . . . . . . . . 101 FERR# (Floating-Point Error) . . . . . . . . . . . . . . . . . . . . . . . 102 FLUSH# (Cache Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 HIT# (Inquire Cycle Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 HITM# (Inquire Cycle Hit To Modified Line) . . . . . . . . . . . 104 HLDA (Hold Acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . 105 HOLD (Bus Hold Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 105 IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . 106 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 INTR (Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 108 INV (Invalidation Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 108 KEN# (Cache Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 LOCK# (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 M/IO# (Memory or I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 NA# (Next Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . 112 PCD (Page Cache Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 113 PCHK# (Parity Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
iv
Contents
21918B/0 -- October 1999
AMD-K6®-III Processor Data Sheet
4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 4.50 4.51 4.52 4.53 4.54
PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 RSVD (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . 117 SMIACT# (System Management Interrupt Active) . . . . . . 118 STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 TRST# (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 VCC2DET (VCC2 Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 VCC2H/L# (VCC2 High/Low) . . . . . . . . . . . . . . . . . . . . . . . . 121 W/R# (Write/Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 WB/WT# (Writeback or Writethrough) . . . . . . . . . . . . . . . . 123
5
Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.1 5.2 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 129 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Data-NA# Requested. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Pipeline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Pipeline Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Memory Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Single-Transfer Memory Read and Write . . . . . . . . . . . . . . . 132 Misaligned Single-Transfer Memory Read and Write . . . . . 134 Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . 136 Burst Writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Misaligned I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . 141 Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 142 Hold and Hold Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . 142 HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . 144 HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 146 AHOLD-Initiated Inquire Miss. . . . . . . . . . . . . . . . . . . . . . . . 148 AHOLD-Initiated Inquire Hit to Shared or Exclusive Line. 150 AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . 152 AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Bus Backoff (BOFF#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Locked Operation with BOFF# Intervention . . . . . . . . . . . . 160
5.3
5.4
5.5
Contents
v
Others parts begin by am
AM-1 AM-2 AM-3 AM-4 AM-5 AM-6 AM-7 AM-8 AM-9 AM-10 AM-11 AM-12 AM-13 AM-14 AM-15 AM-16 AM-17 AM-18 AM-19 AM-20 AM-21 AM-22 AM-23 AM-24 AM-25 AM-26 AM-27 AM-28 AM-29 AM-30 AM-31 AM-32 AM-33 AM-34 AM-35 AM-36 AM-37 AM-38 AM-39 AM-40 AM-41 AM-42 AM-43 AM-44 AM-45 AM-46 AM-47 AM-48 AM-49 AM-50 AM-51 AM-52 AM-53 AM-54 AM-55 AM-56 AM-57 AM-58 AM-59 AM-60 AM-61 AM-62 AM-63 AM-64 AM-65 AM-66 AM-67 AM-68 AM-69 AM-70 AM-71 AM-72 AM-73 AM-74 AM-75 AM-76 AM-77 AM-78 AM-79 AM-80 AM-81 AM-82 AM-83 AM-84 AM-85 AM-86 AM-87 AM-88 AM-89 AM-90 AM-91 AM-92 AM-93 AM-94 AM-95 AM-96 AM-97 AM-98 AM-99 AM-100 AM-101 AM-102 AM-103 AM-104 AM-105
|
|
|
