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Part: ACT-SF512K32N-39P5I
Category:
Memory
-> Flash
Description: Act-sf512k32 High Speed 512kx32 SRAM / 512kx32 Flash Multichip Module
Company: Aeroflex Circuit Technology
Datasheet: Download ACT-SF512K32N-39P5I datasheet File size : 445 kB
Request For quote: Find where to buy ACT-SF512K32N-39P5I
Datasheet text preview:
ACT-SF512K32 High Speed 512Kx32 SRAM / 512Kx32 Flash Multichip Module
CIRCUIT TECHNOLOGY
FEATURES
4 512K x 8 SRAMs & 4 512K x 8 Flash Die in One MCM s Access Times of 25ns, 35ns (SRAM) and 60ns, 70ns, 90ns (Flash) s Organized as 512K x 32 of SRAM and 512K x 32 of Flash Memory with Common Data Bus s Low Power CMOS s Input and Output TTL Compatible Design s MIL-PRF-38534 Compliant MCMs Available s Decoupling Capacitors and Multiple Grounds for Low Noise s Commercial, Industrial and Military Temperature Ranges s Industry Standard Pinouts s TTL Compatible Inputs and Outputs s Packaging Hermetic Ceramic q 66Lead, PGA-Type, 1.385"SQ x 0.245"max, Aeroflex code# "P1,P5 with/without shoulders)" q 68Lead, Dual-Cavity CQFP(F2), 0.88"SQ x .20"max (.18 max thickness available, contact factory for details) (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint)
s s
www.aeroflex.com
FLASH MEMORY FEATURES
Sector Architecture (Each Die) q 8 Equal Sectors of 64K bytes each
q Any
combination of sectors can be erased with one command sequence
+5V Programing, +5V Supply s Embedded Erase and Program Algorithms s Hardware and Software Write Protection s Page Program Operation and Internal Program Control Time. s 10,000 Erase/Program Cycles
s
A E RO
F
LE
X LA
B
S
I NC .
C
IS01 O 90
E
RTIFIE D
Block Diagram PGA Type Package(P1 & P5) & CQFP(F2)
FWE1 SWE1 OE A0A18 SCE FCS FWE2 SWE2 FWE3 SWE3 F W E 4 SWE4 PIN DESCRIPTION I/O0-31 A018 F W E1 - 4 Data I/O Address Inputs Flash Write Enables
SWE1-4 SRAM Write Enables
512K X 8 FLASH 512K X 8 SRAM 512K X 8 FLASH 512K X 8 SRAM 512K X 8 FLASH 512K X 8 SRAM 512K X 8 FLASH 512K X 8 SRAM
FCE SCE OE NC VCC GND
Flash Chip Enable SRAM Chip Enable Output Enable Not Connected Power Supply Ground
I/O0-7
I/O8-15
I/O16-23
I/O24-31
eroflex Circuit Technology - Advanced Multichip Modules © SCD3852 REV A 5/20/98
Absolute Maximum Ratings
Symbol TC TSTG VG TL Parameter Flash Data Retention Flash Endurance (Write/Erase Cycles) 10 Years 10,000 Operating Temperature Storage Temperature Maximum Signal Voltage to Ground Maximum Lead Temperature (10 seconds) Rating Range -55 to +125 -65 to +150 -0.5 to +7 300 Units °C °C V °C
Normal Operating Conditions
Symbol VCC VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Minimum +4.5 +2.2 -0.5 Maximum +5.5 VCC + 0.3 +0.8 Units V V V
Capacitance
(VIN = 0V, f = 1MHz, TC = 25°C) Symbol Parameter CAD CO E CWE1-4 CCE CI / O A0 A18 Capacitance OE Capacitance F/S Write Enable Capacitance F/S Chip Enable Capacitance I/O0 I/O31 Capacitance Maximum 80 80 30 50 30 Units pF pF pF pF pF
This parameter is guaranteed by design but not tested
DC Characteristics
(VCC = 5.0V, VSS = 0V, TC = -55°C to +125°C) Parameter Input Leakage Current Output Leakage Current Sym ILI ILO Conditions VCC = Max, VIN = 0 to VCC FCE = SCE = VIH, OE = VIH, VOUT = 0 to VCC Min M a x Units 10 10 550 80 0.4 2.4 260 300 0.45 0.85 x VCC 3.2 4.2 µA µA mA mA V V mA mA V V V
SCE = VIL, OE = VIH, f = 5MHz, VCC = SRAM Operating Supply Current x 32 IC C x 3 2 Max, FCE = VIH Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash Vcc Active Current for Read (1) Flash Vcc Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Low Vcc Lock Out Voltage ISB VOL VOH ICC1 ICC2 VOL VOH1 VLKO FCE = SCE = VIH, OE = VIH, f = 5MHz, VCC = Max IOL = 8 mA, VCC = Min, FCE = VIH IOH = -4.0 mA, , VCC = Min, FCE = VIH FCE = VIL, OE = VIH, SCE = VIH FCE = VIL, OE = VIH, SCE = VIH IOL = 12 mA, VCC = Min, SCE = VIH IOH = -2.5 mA, , VCC = Min, SCE = VIH
Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
Aeroflex Circuit Technology
2
SCD3852 REV A 5/20/98
Plainview NY (516) 694-6700
SRAM AC Characteristics
(VCC = 5.0V, VSS= 0V, Tc= -55°C to +125°C)
Read Cycle
Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change Output Enable to Output Valid Chip Select to Output in Low Z * Output Enable to Output in Low Z * Chip Deselect to Output in High Z * Output Disable to Output in High Z * * Parameters guaranteed by design but not tested Symbol tRC tAA tACE tOH tOE tCLZ tOLZ tCHZ tOHZ 2 0 12 12 0 12 4 0 15 15 025 Min Max 25 25 25 0 25 035 Min Max 35 35 35 Units ns ns ns ns ns ns ns ns ns
Write Cycle
Parameter Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Output Active from End of Write * Write to Output in High Z * Data Hold from Write Time Address Hold Time * Parameters guaranteed by design but not tested Symbol t WC t CW tAW tDW tWP tAS tOW tWHZ tDH tAH 0 0 025 Min Max 25 17 17 13 17 2 4 13 0 0 035 Min Max 35 25 25 20 25 2 4 15 Units ns ns ns ns ns ns ns ns ns ns
Truth Table
Mode Standby Read Output Disable Write SCE H L L L OE X L H X SWE X H H L Data I/O High Z Data Out High Z Data In Power Standby Active Active Active
Aeroflex Circuit Technology
3
SCD3852 REV A 5/20/98
Plainview NY (516) 694-6700
Timing Diagrams -- SRAM
Read Cycle Timing Diagrams Read Cycle 1 (SCE = OE = VIL, SWE = VIH)
tRC A 0-18 tAA t OH D I/O Previous Data Valid Data Valid SCE tAS SWE
SEE NOTE
Write Cycle Timing Diagrams Write Cycle (SWE Controlled, OE = VIH)
tWC A 0-18 tAW tCW tAH
tWP
tWHZ
tDW Data Valid
tOW tDH
D I/O
Read Cycle 2 (SWE = VIH)
t RC A 0-18 tAA SCE tACE tCLZ
SEE NOTE
Write Cycle (SCE Controlled, OE = VIH )
tWC A0-18 tAW tCHZ
SEE NOTE
tAH tCW
t AS SCE
OE tWP tOE tOLZ
SEE NOTE
t OH Z
SEE NOTE
SWE tDW D I/O Data Valid tDH
D I/O
High Z
Data Valid
UNDEFINED
DON'T CARE
Note: Guaranteed by design, but not tested.
AC Test Circuit
Current Source IOL
AC Test Conditions
Parameter Typical 0 3.0 5 1.5 Units V ns V
To Device Under Test CL = 50 pF
VZ ~ 1.5 V (Bipolar Supply)
Input Pulse Level Input Rise and Fall Input and Output Timing Reference Level
IOH Current Source
Notes: 1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance.
4
Aeroflex Circuit Technology
SCD3852 REV A 5/20/98
Plainview NY (516) 694-6700
Flash AC Characteristics Read Only Operations
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output High Z (1) Output Enable High to Output High Z(1) Output Hold from Address, CE or OE Change, Whichever is First Note 1. Guaranteed by design, but not tested
Symbol 60 70 90 Units JEDEC Stand'd Min Max Min Max Min Max
tAVAV tAVQV t E L QV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE t OE tDF tDF tOH 0 60 60 60 30 20 20 0 70 70 70 35 20 20 0 90 90 90 35 20 20 ns ns ns ns ns ns ns
Flash AC Characteristics Write / Erase / Program Operations, FWE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Write Cycle Time Chip Enable Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation Sector Erase Time Read Recovery Time before Write Vcc Setup Time Chip Programming Time Chip Enable Hold Time Chip Erase Time 1. Toggle and Data Polling only.
Symbol JEDEC Stand'd
tAVAC tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tWC tCE tWP tAS tDS tDH tAH tWPH
60 70 90 Min Max Min Max Min Max
60 0 40 0 40 0 45 20 14 TYP 30 0 0 50 50 50 10 120 120 50 50 10 120 70 0 45 0 45 0 45 20 14 TYP 30 0 50 90 0 45 0 45 0 45 20 14 TYP 30
Units
ns ns ns ns ns ns ns ns µs Sec µs µs Sec ns Sec
tGHWL
tVCE tOEH 1 tWHWH3
10
Flash AC Characteristics Write / Erase / Program Operations, FCE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Write Cycle Time Write Enable Setup Time Chip Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Enable Pulse Width High Duration of Byte Programming Sector Erase Time Read Recovery Time Chip Programming Time Chip Erase Time
Symbol JEDEC Stand'd
tAVAC tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tWC tWS tCP tAS tDS tDH tAH tCPH
60 70 90 Min Max Min Max Min Max
60 0 40 0 40 0 45 20 14 TYP 30 0 50 0 50 120 70 0 45 0 45 0 45 20 14 TYP 30 0 50 120 90 0 45 0 45 0 45 20 14 TYP 30
Units
ns ns ns ns ns ns ns ns µs Sec ns Sec Sec
tGHEL
tWHWH3 5
120
Aeroflex Circuit Technology
SCD3852 REV A 5/20/98
Plainview NY (516) 694-6700
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