Full militarized QED RM5270 microprocessor Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle
150, 200 MHz operating frequencies Consult Factory for latest speeds 260 Dhrystone2.1 MIPS SPECfp95 5.3
High performance system interface compatible with R4600, R4700 and R5000
cycle repeat rate for common single precision operations and some double precision operations q Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations q Single cycle repeat rate for single precision combined multiplyadd operation
multiplexed system address/data bus for optimum price/ performance with to 100 MHz operating frequency q High performance write protocols maximize uncached write bandwidth q Supports clock divisors q 5V compatible I/O's q IEEE 1149.1 JTAG boundary scan
point multiply-add instruction increases performance in signal processing and graphics applications q Conditional moves to reduce branch frequency q Index address modes (register + register)
instruction - 2 way set associative data - 2 way set associative q Virtually indexed, physically tagged q Write-back and write-through on per page basis q Pipeline restart on first double for data cache misses
DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction q I and D cache locking by set q Optional dedicated exception vector for interrupts
Fully static CMOS design with power down logic
reduced power mode with WAIT instruction Watts typical 3.3V 200 MHz
associative joint TLB (shared by I and D translations) q 48 dual entries map 96 pages q Variable page size in 4x increments)
208-lead CQFP, cavity-up package (F17) 208-lead CQFP, inverted footprint (F24), Intended to duplicate the commercial QED footprint 179-pin PGA package (Future Product) (P10)
eroflex Circuit Technology RISC TurboEngines For The Future © SCD5270 REV 1 12/22/98
The is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 64-bit system interface with support for an optional external secondary cache. The ACT5270 can issue both an integer and a floating point instruction in the same cycle. The ACT5270 is ideally suited for high-end emb edded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization.The ACT5270 is also applicable to the low end workstation market where its balanced integer and floating-point performance and direct support for a large secondary cache (up to 2MB) provide outstanding price/performance
floating-point operations. Like the R5000, the ACT5270 does virtual to physical translation in parallel with cache access.
As part of the ACT52xx family, the ACT5270 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the ACT5270 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in the QED RM5270 datasheet, these instructions are integer multiply-accumulate and 3-operand integer multiply. The ACT5270 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/ divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/divide operations, and the program counter(PC).
The ACT5270 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the ACT5270 are briefly described below.
The ACT5270 has thirty-two general purpose registers with register location 0 hard wired to zero. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.
The ACT5270 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/ store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the ACT5270 provides unparalleled price/performance in computationally intensive embedded applications.
The ACT5270 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle.
Like all MIPS ISA processors, the ACT5270 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits.
For additional Detail Information regarding the operation of the Quantum Effect Design (QED) RISCMark ACT5270TM, 64-Bit Superscalar Microprocessor see the latest QED datasheet (Revision 1.1 July 1998).
For integer operations, loads, stores, and other non-floating-point operations, the ACT5270 uses the simple 5-stage pipeline also found in the ACT52xx family, R4600, R4700, and R5000. In addition to this standard pipeline, the ACT5270 uses an extended seven stage pipeline for
Note: Pin rotation is opposite of QEDs PQUAD due to cavity-up construction.