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Details, datasheet, quote on part number:3X38FTR
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Preliminary Data Sheet June 2000
3X38FTR 256-Pin PBGA OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX
Overview
The 3X38 256-Pin PBGA is an eight-channel, singlechip complete transceiver designed specifically for dual-speed 10Base-T, 100Base-TX, and 100BaseFX switches and repeaters. It supports simultaneous operation in three separate IEEE* standard modes: 10Base-T, 100Base-TX, and 100Base-FX. The 3X38 uses 0.25 µm low-power CMOS to achieve extremely low power dissipation and operates from single 3.3 V power supply. Each channel implements the following:
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Autopolarity detection and correction. Adjustable squelch level for extended line length capability (two levels). On-chip filtering eliminates the need for external filters. Half- and full-duplex operations.
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100 Mbits/s TX Transceiver
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10Base-T transceiver function of IEEE 802.3. 100Base-TX transceiver function of IEEE 802.3u. 100Base-FX transceiver function of IEEE 802.3u.
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Compatible with IEEE 802.3u PCS (clause 23), PMA (clause 24), autonegotiation (clause 28), and PMD (clause 25) specifications. Compatible with the reduced MII (RMII) specification of the RMII consortium version 1.2. Selectable 7-pin RMII, 2-pin SMII (serial MII). Scrambler/descrambler bypass. Selectable carrier sense signal generation (CRS) asserted during either transmission or reception in half duplex (CRS asserted during reception only in full duplex). Full- or half-duplex operations. On-chip filtering and adaptive equalization that eliminates the need for external filters.
Autonegotiation of IEEE 802.3u.
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MII management of IEEE 802.3u.
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The 3X38 supports operations over two pairs of unshielded twisted-pair (UTP) cable (10Base-T and 100Base-TX) and over fiber-optic cable (100BaseFX).
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It has been designed with a flexible system interface that allows configuration for optimum performance and effortless design. The individual per-port system interface can be configured as 10 Mbits/s or 100 Mbits/s reduced MII (RMII) or 10 Mbits/s or 100 Mbits/s serial MII (SMII).
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100 Mbits/s FX Transceiver
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Features
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Pseudo-ECL compatible input/output for 100BaseFX support (with fiber-optic signal detect). Compatible with IEEE 802.3U 100Base-FX standard. Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL (PECL) data: -- No additional data pins required. -- Reuses existing 3X38 pins for fiber-optic signal detect (FOSD) inputs.
10 Mbits/s Transceiver
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Compatible with IEEE 802.3 10Base-T standard for category 3 unshielded twisted-pair (UTP) cable. Compatible with the reduced MII (RMII) specification of the RMII consortium version 1.2. Selectable 7-pin RMII or 2-pin serial MII (SMII).
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* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
3X38FTR 256-Pin PBGA OCTAL-FET for 10Base-T/100Base-TX/FX
Preliminary Data Sheet June 2000
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Features (continued)
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Single 50 MHz/125 MHz clock input in RMII and SMII modes, respectively. Suppor ts half- and full-duplex operations. Provides four LED status signals: -- Activity (transmit or receive). Optional LED blink mode (500 ms on, 500 ms off or 2.5 s on, 2.5 s off) or pulse stretch mode (40 ms--80 ms). -- Full duplex or collision, automatically configured. -- Link integrity. -- Speed indication. Internally generated power-on-reset configures 3X38 automatically on powerup. Serial LED output stream for additional status monitoring. Bicolor LED mode. LED drivers on-chip (8 mA--10 mA). Drivers can be turned off when LED is not used (power saving). Per-channel powerdown mode for 10 Mbits/s and 100 Mbits/s operation. Loopback for 10 Mbits/s and 100 Mbits/s operation. Internal pull-up or pull-down resistors to set default configuration during powerup. 0.25 µm low-power CMOS technology. 256-pin PBGA package. JTAG boundary scan. Single 3.3 V power supply.
Fiber mode automatically configures port: -- Disables autonegotiation. -- Disables 10Base-T. -- Enables 100Base-FX far-end fault signaling. -- Disables MLT-3 encoder/decoder. -- Disables scrambler/descrambler. FX mode enable is pin- or register-selectable on an individual per-port basis.
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Gen e ra l
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Low power dissipation (<0.4 W per port). Autonegotiation (IEEE 802.3u, clause 28): -- Fast link pulse (FLP) burst generator. -- Arbitration function. Suppor ts the station management protocol and frame format (clause 22): -- Basic and extended registers. -- Supports next page mode. -- Accepts preamble suppression. -- Maskable status interrupts. -- 12.5 MHz MDC clock rate. Suppor ts the following management functions via pins if MII station management is unavailable: -- Speed select. -- Scrambler/descrambler bypass. -- Full duplex. -- No link pulse mode. -- Carrier sense select. -- Autonegotiation. -- FX mode select.
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Lucent Technologies Inc.
Preliminary Data Sheet June 2000
3X38FTR 256-Pin PBGA OCTAL-FET for 10Base-T/100Base-TX/FX
Table of Contents
Contents Page
Over view ......... 1 Features.......... 1 10 Mbits/s Transceiver ......... 1 100 Mbits/s TX Transceiver........... 1 100 Mbits/s FX Transceiver........... 1 General ........ 2 Description...... 5 RMII Mode ............ 5 SMII Mode ............ 5 LED Control .......... 5 Clocking ....... 5 FX Mode ...... 5 Single-Channel Detail Functions ........ 7 Block Diagrams..... 8 Pin Information ...... 10 Pin Diagram for RMII Mode ........ 10 Pin Diagram for SMII Mode ........ 11 Pin Maps.... 15 Pin Descriptions..... 16 Functional Description .......... 27 Reduced Media Independent Interface (RMII).... 27 RMII/SMII Interface............ 29 Media Independent Interface (MII)--Internal ...... 31 100Base-X Module ............ 32 100Base-TX Transceiver.... 36 10Base-T Module .............. 37 Operation Modes ...... 37 LED Operational Modes .... 39 Reset Operation........ 43 MII Station Management ...... 44 Basic Operation ........ 44 Unmanaged Operations..... 45 Register Information ............. 46 Register Descriptions ........ 46 Absolute Maximum Ratings ........... 56 Clock Timing .......... 57 Outline Diagram..... 63 256-Pin PBGA .......... 63
Tables
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Table 1. 3X38 Signal in Alphanumeric Sequence According to Pin Number........ 12 Table 2. 3X38 RMII/SMII Pin Map....... 15 Table 3. RMII/SMII Interface Pins ....... 16 Table 4. MII Management .... 17 Table 5. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins..... 18 Table 6. LED and Configuration Pins........... 18 Table 7. Table Test Mode Pins ...... 24 Table 8. Clock, Reset, FOSD, and Special Configuration Pins ..... 25 Table 9. Power, Ground, and No Connects........... 26 Table 10. Receive Data/Status Encoding..... 30 Table 11. Symbol Code Scrambler ............. 33 Table 12. LED Modes .......... 40 Table 13. Serial LED Pin Descriptions ......... 41 Table 14. Serial LED Port Order ... 41 Table 15. Bicolor Mode ........ 42 Table 16. Bicolor LED Mode Descriptions ............ 43 Table 17. MII Management Frame Format............ 44
Lucent Technologies Inc.
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3X38FTR 256-Pin PBGA OCTAL-FET for 10Base-T/100Base-TX/FX
Preliminary Data Sheet June 2000
Table of Contents (continued)
Tables Page
Table 18. MII Management Frames--Field Descriptions......44 Table 19. PHY Addresses .... 45 Table 20. Output Pins ........... 45 Table 21. Summary of Management Registers (MR) ........... 46 Table 22. MR0--Control Register Bit Descriptions......46 Table 23. MR1--Status Register Bit Descriptions .......... 47 Table 24. MR2, MR3--PHY Identification Registers (1 and 2) Bit Descriptions....48 Table 25. MR4--Autonegotiation Advertisement Register Bit Descriptions .......... 48 Table 26. MR5--Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions.......49 Table 27. MR5--Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions.........49 Table 28. MR6--Autonegotiation Expansion Register Bit Descriptions........50 Table 29. MR7--Next Page Transmit Register Bit Descriptions .... 50 Table 30. MR20--LED and FIFO Configuration .... 51 Table 31. MR21--RXER Counter ........ 51 Table 32. MR28--Device-Specific Register 1 (Status Register) Bit Descriptions..52 Table 33. MR29--Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions .......... 53 Table 34. MR30--Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions ...... 54 Table 35. MR31--Device-Specific Register 4 (Quick Status) Bit Descriptions......55 Table 36. Absolute Maximum Ratings .......... 56 Table 37. Operating Conditions ..... 56 Table 38. dc Characteristics .......... 56 Table 39. System Clock (RMII Mode) ........... 57 Table 40. Management Clock ........ 57 Table 41. RMII Receive Timing......58 Table 42. RMII Transmit Timing ..... 58 Table 43. Transmit Timing.....59 Table 44. SMII Timing...........59 Table 45. Receive Timing .....60 Table 46. Reset and Configuration Timing ............61 Table 47. PMD Characteristics ...... 62
Figures
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Figure 1. 3X38 Device Overview ..... 6 Figure 2. 3X38 Single-Channel Detail Functions .... 7 Figure 3. Typical Single-Channel Twisted-Pair (TP) Interface ......... 8 Figure 4. Typical Single-Channel Fiber-Optic (FX) Interface ........... 9 Figure 5. 3X38 Pinout for RMII Mode...........10 Figure 6. 3X38 Pinout for SMII Mode ........... 11 Figure 7. Functional Description ... 27 Figure 8. RMII Receive Timing from Internal MII Signals.....28 Figure 9. SMII Connection Diagram ............. 29 Figure 10. Receive Sequence Diagram ....... 29 Figure 11. Transmit Sequence Diagram ....... 30 Figure 12. 100Base-X Data Path ........ 32 Figure 13. 10Base-T Module Data Path.......37 Figure 14. Timing Diagram............42 Figure 15. Hardware Reset Configuration....43 Figure 16. System Clock ...... 57 Figure 17. Management Clock ...... 57 Figure 18. RMII Receive Timing....58 Figure 19. RMII Transmit Timing ... 58 Figure 20. Transmit Timing ............ 59 Figure 21. SMII Timing ......... 59 Figure 22. Receive Timing ............ 60 Figure 23. Reset and Configuration Timing...........61 Figure 24. PMD Characteristics ....62
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Lucent Technologies Inc.
Preliminary Data Sheet June 2000
3X38FTR 256-Pin PBGA OCTAL-FET for 10Base-T/100Base-TX/FX
LED Control
LEDs can be accessed in one of the following modes:
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Description
RMII Mode
The reduced media independent interface (RMII) is a low pin count interface specification promulgated by the RMII consortium. This specification reduces the total number of pins from 16 for the IEEE 802.3u MII interface to seven for the RMII. Architecturally, the RMII specification provides for an additional reconciliation sublayer on either side of the MII but, in the 3X38, has been implemented in the absence of the MII. The management interface (MDIO/MDC) remains identical to that defined in IEEE 802.3u. The RMII specification has the following characteristics:
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Serial mode. In this mode, all of the LEDs are timedivision multiplexed onto one pin, with a second pin acting as the clock and a third as a strobe. All LEDs and all channels share the same pins. Parallel mode. In this mode, each LED and each channel has its own pin. There is a total of four LED pins per channel for a total of 32 pins. Bicolor mode. In this mode, each channel has two outputs to control a bicolor LED. One LED can be used for each port, indicating link and activity.
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In all modes, the LEDs can be operated as follows:
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It supports 10 Mbits/s and 100 Mbits/s data rates. A single 50 MHz clock reference is sourced from MAC to PHY or from an external shared source. It provides independent 2-bit wide transmit and receive data paths.
LED stretch. LED blink. No stretch or blink.
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Clocking
The 3X38 operates with a 50 MHz clock input when in the RMII mode, and with a 125 MHz clock input when in the SMII mode.
SMII Mode
The serial media independent interface (SMII) is a low pin count interface specification promulgated by Cisco*. This specification reduces the total number of pins from 16 for the IEEE 802.3u MII interface to two for the SMII. Architecturally, the SMII specification provides for an additional reconciliation sublayer on either side of the MII but, in the 3X38, has been implemented in the absence of the MII. The management interface (MDIO/MDC) remains identical to that defined in IEEE 802.3u. The SMII specification has the following characteristics:
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FX Mode
Each individual port of the 3X38 can be operated in 100Base-FX mode by selecting it through the pin program option (FX_MODE_EN[7:0]), or through the register bit (register 29, bit 0). When operating in FX mode, the twisted-pair I/O pins are reused as the fiber-optic transceiver I/O data pins, and the fiber-optic signal detect (FOSD) inputs are enabled. When a port is placed in FX mode, it will automatically configure the port for 100Base-FX operation (and the register bit control will be ignored) such that:
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It supports 10 Mbits/s and 100 Mbits/s data rates. A single 125 MHz clock reference is sourced from MAC to PHY or from an external shared source. It provides independent serial transmit and receive data paths.
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The far-end fault signaling option will be enabled. The MLT-3 encoding/decoding will be disabled. Scrambler/descrambler will be disabled. Autonegotiation will be disabled. The signal detect inputs will be activated. 10Base-T will be disabled.
* Cisco is a registered trademark of Cisco Systems.
Lucent Technologies Inc.
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