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Part: NEWPORT
Category:
Communication
-> ISDN
-> S/T-Interface
Description: Newport Atm Access Soc
Company: Agere Systems
Datasheet: Download NEWPORT datasheet File size : 105 kB
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Datasheet text preview:
Preliminary Data Sheet August 2001
TAAD08JU2 Newport T1/E1/J1/J2 ATM Processor
1 Features
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2 Physical
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System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station (BTS), base station controller BSC), and remote access concentrator (RAC) applications. IC provides an integrated octal framer that supports T1/E1/J1/J2 formats. Supports inverse multiplexing for ATM (IMA) over selected group and link mappings ranging from four two-link groups up to one eight-link group per ATM Forum AF-PHY-0086.001. Integrates an ATM adaptation layer 2 (AAL2) segmentation and reassembly (SAR) function for support of low-speed data or voice traffic per ITU I.363.2. Provides AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS) connection identifier (CID) multiplexing per ITU I.366.1. Enables ATM layer user network interface (UNI) or IMA mode, selectable on a per-link basis for flexible transport of delay critical voice and data traffic. Guarantees QoS for a variety of traffic types (including delay-sensitive voice, real-time data, non-real-time data, and signaling information) through an advanced hierarchical three-level priority scheduler and per-VC queueing. Supports 2047 AAL2 CIDs. Supports 2048 high-speed data connections or virtual circuits (VCs) via embedded context memory; filters control cells and accepts control cells via a host microprocessor interface. Software package includes the following: -- Software device manager source code (Cbased device manager ready-to-use with host RTOS) and firmware for embedded controller (executable binary). -- User manual available for device manager software. Designed in 0.16 µm, low-power CMOS technology.
3.3 V digital I/O compatibility; 1.5 V core power 520 enhanced ball-grid array (EBGA) package 40 oC to +85 oC temperature range
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3 Standards
ITU I.363.2 ITU I.366.1 ITU I.363.5 ITU I.432 ITU I.361 ITU I.371 ITU G.703 ITU G.704 ITU G.804 ITU G.732 ITU G.706 ITU I.610 ITU G.775 ITU G.733 ITU G.735 ITU G.965 ITU O.162 ANSI* T1.403 ANSI T1.231 ATM Forum af-phy-0086.001 ATM Forum af-phy-0029.000 ATM Forum af-phy-0039.000 ATM Forum Traffic Management 4.1 ETS 300.417-1-1 TR-NWT-000170
* ANSI is a registered trademark of American National Standards Institute, Inc.
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TAAD08JU2 Newport T1/E1/J1/J2 ATM Processor Table of Contents
Contents
1 2 3 4 5 6 7 8 9 10 11 12 13 2
Preliminary Data Sheet August 2001
Page
Features ........ 1 Physical ........ 1 Standards .............. 1 Description ........... 16 Pin Definitions ...... 17 Pin Description.....17 Package Pin Layout......25 Block Diagram ..... 31 Functional Overview ..... 32 9.1 Receive Direction Data Flow.......32 9.1.1 PHY Layer.............32 9.1.2 Low-Speed PHY Links ... 32 9.1.3 Medium-Speed PHY Links ............ 33 9.1.4 High-Speed PHY Links .. 33 9.1.5 TC and IMA Layers ........ 33 9.1.6 ATM Layer.............34 9.1.7 AAL Engine ........... 34 9.1.8 Embedded Device Controller ........ 35 9.2 Transmit Direction Data Flow......35 9.2.1 SSCS/AAL Layer Interaction.........35 9.2.2 ATM Layer.............35 9.2.3 IMA/TC Layer ........ 36 9.2.4 PHY Layer.............36 Modes of Operation ...... 37 10.1 Interface Modes .. 37 10.1.1 UTOPIA-2 Expansion Port Multiplexing Modes .... 37 10.1.2 System Interface Port Multiplexing Modes......38 10.1.3 Line Interface Modes......38 10.2 Device Operating Modes....38 10.2.1 Operating Mode 1: Internal Framer Mode.......39 10.2.2 Operating Mode 2: External PHY/TC Mode .......... 41 10.2.3 Operating Mode 3: SAR Slave Mode ..... 42 10.2.4 Operating Mode Summary ............ 42 Applications ......... 43 11.1 BTS Network Interface Termination ........... 43 11.2 VToA Trunking Application..........46 11.3 Low-Speed ATM Access....47 11.4 AAL2 Crossconnect ........... 47 Submodule Functional Description ....... 48 12.1 Embedded Device Controller (EDC) .......... 48 12.1.1 Introduction ........... 48 12.1.2 Features .......... 48 12.1.3 EDC Functional Description .......... 48 12.1.4 Host Interface........48 12.1.5 Host Interface Signals and Timing ......... 49 12.1.6 Host Interactions ............ 50 Framer Block ....... 53 13.1 Introduction ......... 53 13.2 Features ..... 53 13.3 Framer-to-Line Interface Unit Physical Interface..........54 13.3.1 Clocking Modes.....54 Agere Systems Inc.
Preliminary Data Sheet August 2001
TAAD08JU2 Newport T1/E1/J1/J2 ATM Processor
Table of Contents (continued)
Contents
14 15 13.4 13.5 13.6 13.7 13.8 13.9
Page
Frame Formats....55 Transmit Framer Functions ......... 56 DS1 Transparent Framing Format ............. 56 CEPT 2.048 Basic Frame Structure Transparent Framing Format......57 Receive Framer Nonalignment Mode (DS1/E1)..58 Loss of Frame Alignment Criteria.........58 13.9.1 Frame Bit Errors....58 13.9.2 CRC Errors............58 13.10 Frame Alignment Criteria ............ 58 13.11 Performance Monitoring Functional Integration Into Framer.......59 13.12 Performance Report Message .... 62 13.13 ESF Data Link ..... 64 13.14 Facility Data Link..........64 13.15 Receive Data Link Functional Description .......... 64 13.16 SLC-96 Superframe Receive Data Link ..... 65 13.17 DDS Receive Data Link Stack .... 65 13.18 CEPT; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms) Multiframe Sa Bits Receive Stack ....... 65 13.19 Receive Data Link Stack Idle Modes ......... 65 13.20 Transmit Facility Data Link Functional Description ...... 66 13.21 SLC-96 Superframe Transmit Data Link .... 66 13.22 DDS Transmit Data Link Stack ... 66 13.23 Transmit ESF Data Link Bit-Oriented Messages ......... 66 13.24 CEPT, CEPT Multiframe Transmit Data Link Sa Bits Stack........67 13.25 Transmit Data Link Stack Idle Modes ........ 68 13.26 SLC-96, DDS, or CEPT ESF Frame Alignment .. 68 13.27 Concentration Highway Interface (CHI) ..... 68 13.28 Transmit/Receive System Interface Features ..... 68 13.29 Double NOTFAS System Time-Slot Mode..........69 13.30 Transparent Mode..............69 13.31 Loopbacks ........... 69 13.32 Nominal CHI Timing ........... 70 13.33 CHI Timing with CHI Double Time-Slot Timing (CHIDTS) Mode Enabled .......... 71 13.34 Clocking Scheme ...... 71 Transmission Convergence (TC) Block ......... 72 14.1 Introduction ......... 72 14.2 Features ..... 72 14.3 TC--Receive Direction.......73 14.4 TC--Transmit Direction......73 14.4.1 HEC Generation/Checking............74 14.5 Cell Delineation ... 74 14.6 Cell Payload Scrambling/Descrambling ..... 74 14.7 Cell Mapping ....... 74 14.8 Facility Maintenance .......... 74 14.9 Cell Rate Decoupling ......... 74 14.10 Functionality ........ 75 Inverse Multiplexing for ATM (IMA) Block............76 15.1 Introduction ......... 76 15.2 Features ..... 77 15.3 Multi-PHY UTOPIA Slave Interface............78 15.4 Link Processor .... 78 15.5 Group Processor .......... 79 15.6 Delay Compensation Buffer (DCB) ............ 80 Lucent Technologies--Proprietary Use pursuant to Company instructions 3
Agere Systems Inc.
Others parts begin by ne
NE-1 NE-2 NE-3 NE-4 NE-5 NE-6
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