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Details, datasheet, quote on part number:NPASI
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Product Brief June 2001
PayloadPlusTM Agere System Interface
Introduction
The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full programmability. This combination gives you the programmability of traditional RISC processors with the speed that, until now, only ASICs could deliver. The Agere Systems PayloadPlus product family represents a technology revolution for the construction of intelligent communication equipment with Layer 3 or above processing capabilities. Agere Systems products focus on the wire-speed datapath functions and work in conjunction with physical interface devices, lowspeed microprocessor, and backplane fabric offerings to provide a complete solution for networking and communication applications. The PayloadPlus processor family includes the Fast Pattern Processor (FPP), Routing Switch Processor (RSP), and the Agere System Interface (ASI). The Agere Systems PayloadPlus Processors are designed to handle wire-speed data streams at up to OC-48c rates. Each chip provides a complementary function: the FPP for high-speed classification, the RSP for processing and routing traffic, and the ASI to provide policing, manage state information, and provide a PCI connection to a host processor. The FPP accepts a data stream of protocol data units (PDUs) from an industry-standard POSPHY/UTOPIA Level 3 interface. The PDUs are analyzed and classified, and the FPP outputs the packets and conclusions to the RSP on a POSPHY Level 3 interface.
Agere System Interface
The ASI seamlessly integrates the FPP and RSP with the host processor. The wire-speed data stream operations are performed by the FPP, RSP, and ASI. The host processor is used exclusively for slow path processing--it is not used for pattern recognition, classification, queuing, or traffic management operations. A typical system using the ASI, the FPP, and the RSP is shown in the block diagram in this document.
Features and Benefits of the ASI
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An industry-standard interface to the FPP and RSP for a host microprocessor that allows: -- Centralized initialization and configuration of the FPP, RSP, and physical interfaces. -- Routing and VPI/VCI table updates to the FPP. -- Queue processing updates to the RSP. -- Implementation of routing and management protocols. -- Exception handling. High-speed, flow-oriented state maintenance for the FPP, including: -- RMON statistics gathering. -- Packet sequence checking. -- Packet time stamping. -- ATM and Frame Relay policing at up to OC-48c rates. -- An 8-bit POS/PHY interface to send packets to the FPP and receive packets from the RSP.
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Product Brief June 2001
NPASI Agere System Interface
Physical Interface
P O S -P H Y U T O P IA
FPP
RSP
P O S -P H Y U T O P IA
Fabric Interface Controller
Fabric
C o n fig u r a tio n B u s FBI
ASI
8 - b it PO S - P H Y P C I to H o s t CPU
8 - b i t PO S - P H Y
S y s t e m O v e r v ie w
Applications
You can use the ASI in the following applications:
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Configuration Bus Interface--The ASI's 8-bit Configuration Bus allows the host processor to configure the FPP and RSP, and up to six additional devices.
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Communicate with the host control processor using a Peripheral Component Interconnect (PCI) bus. Send and receive protocol data units (PDUs) using an 8-bit POS/PHY interface. Service FPP function calls using an ALU, SRAM, and a high-speed 32-bit Functional Bus Interface (FBI). Maintain state information on PDUs, flows, or connections using optional SRAM. Police ATM and Frame Relay connections. Configure up to eight devices using an 8-bit Configuration Bus.
FPP Function Calls to the ASI
The FPP is programmed using the Functional Programming Language (FPL). FPL code can invoke functions that are executed on external hardware, extending the capabilities of the FPP. The ASI contains an ALU and an SSRAM interface state buffer used to implement functions that are invoked by FPL code. These functions include:
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ASI Interfaces
The ASI supports the following interfaces:
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Policing ATM and Frame Relay traffic. RMON operations. Time-stamping PDUs. Capturing and maintaining statistics. PDU sequence checking for Frame Relay reassembly.
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PCI Interface--The ASI has a 64-bit, 66-MHz PCI interface that is a full master/slave implementation with DMA and interrupt support. POS/PHY Interface--The ASI's 8-bit POS/PHY interfaces operate at up to 133 MHz and allow the host processor to receive PDUs from the RSP and send PDUs to the FPP. Functional Bus Interface (FBI)--The ASI's 32-bit Functional Bus Interface extends the capabilities of the FPP by allowing the FPP to make function calls that are executed by the ASI. SSRAM Memory Interfaces--Two industry-standard 32-bit memory interfaces.
ASI Policing Capabilities
The ASI supports high-speed policing of ATM and Frame Relay traffic. It can use one of several leaky-bucket configurations. The default configuration uses the GCRA algorithm defined by the ATM Traffic Management Specification, version 4.0. When the FPL program calls the policing function for a PDU, the ASI checks for compliance and returns flags that indicate whether the cell or frame is compliant. The FPL program then determines the action to take. For example, the FPL program could simply flag noncompliant PDUs, or it could discard them. The ASI supports policing at rates up to OC-48c.
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Product Brief June 2001 ASI Configuration Capabilities
The ASI is designed to allow the host processor to configure up to eight devices using the Configuration Bus. The ASI Configuration Bus Interface is compatible with both the Intel and Motorola bus formats, allowing configuration of third party devices such as framers and physical interfaces. The ASI Configuration Bus is used to:
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NPASI Agere Systems Interface
A PCI interface for communicating with the host processor. A high-speed 32-bit Functional Bus Interface (FBI) for servicing FPP function calls. Two ALUs for processing FPP external function requests: one for maintaining state and statistics, and another for policing. Two SSRAM interfaces, to allow memory access for different tasks without contention. Two 8-bit POS-PHY (Level 3) interfaces, one for receiving PDUs from the RSP, an the other for sending PDUs to the FPP. Because these are standard interfaces, they can be connected to other devices. An 8-bit configuration bus for configuring up to eight devices, including the FPP and the RSP.
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Initialize and configure the FPP and RSP. Load the program code for the FPP and RSP. Load the dynamic updates to the FPP tables and the RSP queues. Configure third party external framers and physical interfaces.
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ASI Internal Architecture
How the ASI Works
The ASI performs multiple tasks for the FPP, RSP, and host processor. It is designed to perform these functions and support policing at wire-speed data stream rates of up to OC48c. To meet these requirements, the ASI employs the following components: The block diagram that follows shows the internal architecture of the ASI.
FBI
ALU
FBI Control Logic
Policing Compute Engine SSRAM Interface
Policing SSRAM
Stat e SSRAM
ASI
SSRAM Interface Configuration Bus
To FPP POS-PHY
PDU Data Transmit Interface
P CI Interface
PDU Data Receive Interface
From RSP POS-PHY
PCI to Host Processor
Agere System Interface Internal Block Diagram
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