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Part: ORT8850
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
-> SRAM-based FPGA/PAL
Description: Field-programmable System Chip ( FPSC ) Eight-channel X 850 Mbits/s Backplane Transceiver
Company: Agere Systems
Datasheet: Download ORT8850 datasheet File size : 304 kB
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Datasheet text preview:
Data Sheet August 2001
ORCA® ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
Introduction
Field-programmable system chips (FPSCs) bring a whole new dimension to programmable logic: FPGA logic and an embedded system solution on a single device. Agere Systems Inc. has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer. Built on the Series 4 reconfigurable embedded system-on-chips (SoC) architecture, the ORT8850 family is made up of backplane transceivers containing eight channels, each operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used) full-duplex synchronous interface, with built-in clock and data recovery (CDR) in standard-cell logic, along with up to 600K usable FPGA system gates. The CDR circuitry is a macrocell available from Agere's Smart Silicon macro library, and has already been implemented in numerous applications including ASICs, standard products, and FPSCs to create interfaces for SONET/SDH STS-3/ STM-1, STS-12/STM-4, STS-48/STM-16, and STS192/STM-64 applications. With the addition of protocol and access logic such as protocol-independent framers, asynchronous transfer mode (ATM) framers, packet-over-SONET (POS) interfaces, and framers for HDLC for Internet protocol (IP), designers can build a configurable interface retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge using our PCI soft core. The ORT8850 family offers a clockless high-speed interface for interdevice communication, on a board or across a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET application, all SONET functionality is hidden from the user and no prior networking knowledge is required. The 8850 also offers 8B/10B coding in addition to SONET scrambling. Also included on the device are three full-duplex, highspeed parallel interfaces, consisting of 8-bit data, control (such as start-of-cell), and clock. The interface delivers double data rate (DDR) data at rates up to 311 MHz (622 Mbits/s per pin), and converts this data internal to the device into 32-bit wide data running at half rate on one clock edge. Functions such as centering the transmit clock in the transmit data eye are done automatically by the interface. Applications delivered by this interface include a parallel backplane interface similar to the recently proposed RapidIOTM packet-based interface.
Table 1. ORCA® ORT8850 Family--Available FPGA Logic
Device ORT8850L ORT8850H PFU Rows 26 46 PFU Columns 24 44 Total PFUs 624 2024 FPGA User I/O 296 536 LUTs 4,992 16,192 EBR Blocks 8 16 EBR Bits (K) 74 147 Usable Gates (K) 260--470 530--970
Note: The embedded core and interface are not included in the above gate counts.The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit plus each block has an additional 25K gates. 7K gates are used for each PLL and 50K gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate calculations.
ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver
Data Sheet August 2001
Table of Contents
Contents Page Contents Page
Introduction .........1 Embedded Core Features (Serial).......4 Embedded Core Features (Parallel)....4 Programmable FPGA Features ..5 Programmable Logic System Features .....6 Description..........7 What Is an FPSC? .........7 FPSC Overview .......7 FPSC Gate Counting .....7 FPGA/Embedded Core Interface .....7 ORCA Foundry Development System ............7 FPSC Design Kit ......8 FPGA Logic Overview ....8 PLC Logic .......8 Programmable I/O ....9 Routing ............9 System-Level Features....10 Microprocessor Interface ......10 System Bus ...10 Phase-Locked Loops ............10 Embedded Block RAM ..........10 Configuration ..........11 Additional Information ...........11 ORT8850 Overview .........12 Device Layout ........12 Backplane Transceiver Interface ...12 HSI Interface ..........15 STM Macrocell .......15 8B/10B Encoder/Decoder .....15 FPGA Interface ......15 Byte-Wide Parallel Interface ..........15 FPSC Configuration .....16 Generic Backplane Transceiver Application.....17 Synchronous Transfer Mode (STM) .....17 8B/10B Mode .........17 Backplane Transceiver Core Detailed Description ....18 HSI Macro .....18 STM Transmitter (FPGA Æ Backplane) ........20 STM Receiver (Backplane Æ FPGA) ............23 8B/10B Transmitter (FPGA Æ Backplane) ...30 8B/10B Receiver (Backplane Æ FPGA) .......30 Pointer Mover Block (Backplane Æ FPGA) ..31 Receive Bypass Options and FPGA Interface .......33
Powerdown Mode ....... 33 STM Redundancy and Protection Switching ......... 33 LVDS Protection Switching .. 34 RapidIO Interface to Pi-Sched.......... 34 Overview ...... 34 Receive Cell Interface .......... 34 Transmit Cell Interface ......... 36 Memory Map.... 38 Definition of Register Types .......... 38 Absolute Maximum Ratings..... 55 Recommended Operating Conditions .... 55 Power Supply Decoupling LC Circuit...... 56 HSI Electrical and Timing Characteristics ....... 57 Parallel RapidIO-like Interface Timing Characteristics......... 58 Embedded Core LVDS I/O ...... 59 LVDS Receiver Buffer Requirements ........... 60 Input/Output Buffer Measurement Conditions (on-LVDS Buffer)..... 61 LVDS Buffer Characteristics.... 62 Termination Resistor ............ 62 LVDS Driver Buffer Capabilities .... 62 Pin Information ......... 63 Package Pinouts ......... 77 Package Thermal Characteristics Summary .......... 105 JA ............ 105 JC ............ 105 JC ............ 105 JB ............ 105 FPSC Maximum Junction Temperature ..... 105 Package Thermal Characteristics... 106 Package Coplanarity .... 106 Package Parasitics ....... 106 Package Outline Diagrams.... 107 Terms and Definitions ........ 107 Package Outline Drawings .... 108 352-Pin PBGA ..... 108 680-Pin PBGAM ........ 109 Hardware Ordering Information ...... 110 Software Ordering Information ....... 111
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Agere Systems Inc.
Data Sheet August 2001
ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver
Table of Contents (continued)
List of Figures Page List of Tables Page
Figure 1. . ORCA ORT8850 Block Diagram ....13 Figure 2. . High-Level Diagram of ORT8850 Transceiver ...14 Figure 3. . 8850 with 8B/10B Coding/Decoding ........18 Figure 4. . HSI Functional Block Diagram .......19 Figure 5. . Byte Ordering of Input/Output Interface in STS-12 Mode .....20 Figure 6. . SPE and C1J1 Functionality ...........26 Figure 7. . SPE Stuff Bytes ......27 Figure 8. . Interconnect of Streams for FIFO ...28 Figure 9. . Example of Inter-STM Alignment ...28 Figure 10. . Example of Intra-STM Alignment ..........28 Figure 11. . Example of Twin STS-12 Stream ..........28 Figure 12. . Examples of Link Alignment .........29 Figure 13. . Pointer Mover State Machine .......32 Figure 14. . RapidIO Receive Cell Interface ....35 Figure 15. . RapidIO Transmit Cell Interface ...36 Figure 16. . Sample Power Supply Filter Network for Analog HSI Power Supply Pins ......56 Figure 17. . Receive Parallel Data/Control Timing ...58 Figure 18. . Transmit Parallel Data/Control Timing ..58 Figure 19. . ac Test Loads .......61 Figure 20. . Output Buffer Delays .....61 Figure 21. . Input Buffer Delays ........61 Figure 22. . LVDS Driver and Receiver and Associated Internal Components ...62 Figure 23. . LVDS Driver and Receiver ...........62 Figure 24. . LVDS Driver .........62 Figure 25. . Package Parasitics ......106
Table 1. . ORCA ORT8850 Family-- Available FPGA Logic ......1 Table 2. . Transmitter TOH on LVDS Output (Transparent Mode) .......22 Table 3. . Transmitter TOH on LVDS Output (TOH Insert Mode) .........22 Table 4. . Receiver TOH (Output Parallel Bus) ..25 Table 5. . SPE and C1J1 Functionality .....26 Table 6. . Valid Special Characters .....30 Table 7. . Valid Starting Positions for an STS-Mc .......31 Table 8. . RapidIO Signals to/from FPGA ..........37 Table 9. . Signals Used as Register Bits ...........38 Table 10. . Structural Register Elements ..........39 Table 11. . Memory Map ............40 Table 12. . Memory Map Descriptions .....45 Table 13. . Absolute Maximum Ratings ....55 Table 14. . Recommended Operating Conditions ......55 Table 15. . Absolute Maximum Ratings ....57 Table 16. . Recommended Operating Conditions ......57 Table 17. . Receiver Specifications ....57 Table 18. . Transmitter Specifications ......57 Table 19. . Synthesizer Specifications ......57 Table 20. . Parallel Receive Data/Control Timing .......58 Table 21. . Transmit Parallel Data/Control Timing ......58 Table 22. . Driver dc Data ..........59 Table 23. . Driver ac Data ..........59 Table 24. . Driver Power Consumption .....59 Table 25. . Receiver ac Data .....60 Table 26. . Receiver Power Consumption .........60 Table 27. . Receiver dc Data .....60 Table 28. . LVDS Operating Parameters ...........60 Table 29. . FPGA Common-Function Pin Description ........63 Table 30. . FPSC Function Pin Description .......66 Table 31. . Embedded Core/FPGA Interface Signal Description ....70 Table 32. . ORT8850H Pins That Are Unused in ORT8850L ......77 Table 33. . ORT8850L 352-Pin PBGA Pinout ....78 Table 34. . ORT8850L and ORT8850H 680-Pin PBGAM Pinout ..........88 Table 35. . ORCA ORT8850 Plastic Package Thermal Guidelines .....106 Table 36. . ORCA ORT8850 Package Parasitics .....106 Table 37. . Device Type Options ...... 110 Table 38. . Temperature Options ...... 110 Table 39. . Package Type Options ... 110 Table 40. .ORCA FPSC Package Matrix (Speed Grades) ..... 110
Agere Systems Inc.
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