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Details, datasheet, quote on part number:HDMP-0422
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Datasheet text preview:
Agilent HDMP-0422 Single Port Bypass Circuit with CDR & DV for Fibre Channel Arbitrated Loops Data Sheet
Features · Supports 1.0625 GBd Fibre Channel operation · Supports 1.25 GBd Gigabit Ethernet (GE) operation · Single PBC/CDR in one package · CDR location determined by choice of cable input/output · Amplitude valid and data valid detection (Fibre channel rate only) on FM_NODE[0] input · Equalizers on all inputs · High-speed LVPECL I/O · Buffered Line Logic (BLL) outputs (no external bias resistors required) · 0.46 W typical power at VCC = 3.3 V · 24 Pin, low-cost SSOP package Applications · RAID, JBOD, BTS cabinets · One 2:1 muxes · One 1:2 buffers · 1 N Gigabit serial buffer · N 1 Gigabit serial mux
Description The HDMP-0422 is a Single Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) capability included. This integrated circuit provides a low-cost, lowpower physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP0422, hard disks may be pulled out or swapped while other disks in the array are available to the system. A PBC consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed." When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0422's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC's (e.g. an HDMP-1636A) Rx differential input pins. Data from the Disk Drive Transceiver IC's Tx differential outputs goes to the HDMP-0422's FM_NODE[n]± differential input pins. Figures 2 and 3 show connection diagrams for disk drive array applications.
When the "disk bypassed" mode is selected, the disk drive is either absent or non-functional and the loop bypasses the hard disk. The "disk bypassed" mode is enabled by pulling the BYPASS[n]pin low. Leave BYPASS[n]floating to enable the "disk in loop" mode. HDMP-0422s may be cascaded with other members of the HDMP-04XX/HDMP-05XX family through the appropriate FM_NODE[n]± and TO_NODE[n]± pins to accommodate any number of hard disks (see Figure 4). The unused cells in the HDMP-0422 may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells. An HDMP-0422 may also be used as two 1:1 buffers, one with a CDR and one without. For example, an HDMP-0422 may be placed in front of a CMOS ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming signal (non-CDR paths). In addition, the HDMP-0422 may be configured as one 2:1 multiplexers or as one 1:2 buffers.
HDMP-0422
CAUTION: As with all semiconductor ICs, it is advised that normal static precautionsb be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
FM_NODE[1]
EQU BLL TTL BLL
EQU
1 0
FM_NODE[0] 1 0
TO_NODE[1]
0 1 CDR
DV CPLL
TO_NODE[0]
BYPASS[1]
AV
TTL TTL TTL TTL
TTL
FM_NODE[0]_DV
Figure 1. Block diagram of HDMP-0422.
The HDMP-0422 design allows for CDR placement at any location with respect to a hard disk slot. For example, if hard disk A is connected to PBC cell 1, while BYPASS[0]- is left to float high (see Figure 2), the CDR function will be performed before entering the hard disk at slot A. To obtain a CDR function after slot A (see Figure 3), connect hard disk A to PBC cell 0, while floating BYPASS[1]- high. Refer to Table 1 for both pin connections. CDR The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking feature allows the CDR to lock onto the input data stream without external 2
FM_NODE[0]_AV
BYPASS[0]
MODE_DV
REFCLK
training controls. It does this by continually frequency locking onto the 106.25 MHz reference clock (REFCLK) and then phase locking onto the input data stream. Once bit locked, the CDR generates a high-speed sampling clock. This clock is used to sample or repeat the incoming data to produce the CDR output. The CDR jitter specifications listed in this data sheet assume an input that has been 8B/10B encoded. The CDR will also lock onto data encoded using other algorithms as long as there is DC balance and a sufficient number of transitions. REFCLK INPUT The LVTTL REFCLK input provides a reference oscillator for frequency acquisition of the CDR. The REFCLK frequency should be within ± 100 ppm of one-tenth of
the incoming data rate in baud (106.25 MHz ± 100 ppm for FCAL running at 1.0625 GBd). BLL OUTPUT All TO_NODE[n]± high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL Outputs on the HDMP-0422 are of equal strength and can drive lengthy FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, unused outputs should have their differential pins shorted together with a short PCB trace. If longer traces or transmission lines are connected to the output pins, the lines should be differentially terminated with an appropriate
resistor. The value of the termination resistor should match the PCB trace differential impedance. EQU INPUT All FM_NODE[n]± high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs. The value of the termination resistor should match the PCB trace differential impedance. Alternatively, instead of a single resistor, two resistors in series, with an AC ground between them, can be connected differentially across the FM_NODE[n]± inputs. The latter configuration attenuates high-frequency common mode noise. BYPASS[n]- INPUT The active low BYPASS[n]- inputs control the data flow through the HDMP-0422. All BYPASS pins are LVTTL and contain internal pull-up circuitry. To bypass a port, the appropriate BYPASS[n]- pin should be connected to GND through a 1 k resistor. Otherwise, the BYPASS[n]- inputs should be left to float, as the internal pull-up circuitry will force them high. FM_NODE[0]_DV OUTPUT The Data Valid (DV) block detects if the incoming data at FM_NODE[0]± is valid Fibre Channel data. The DV block checks for sufficient K28.5+ characters (per Fibre Channel framing rules) and for run length violations (per 8B/10B encoding) on the data coming out of the CDR. The FM_NODE[0]_DV output is pulled low if a run length violation (RLV) occurs, or if there are no commas detected (NCD) over a specific time interval. It is pulled high if no errors are detected. 3
A RLV error is defined as any consecutive sequence of 1s or 0s greater than five in the serial bit stream. An NCD error indicates the absence of the seven-bit pattern (0011111) present in the positive disparity comma (K28.5+) character. A K28.5+ character should occur at the beginning of every Fibre Channel frame of 2148 bytes (or 21480 serial bits), as well as many times within and between frames. If this seven-bit pattern is not found within a 215 bit (~31 µs) interval, an NCD error is generated. A counter within the chip tracks the 2 15 bit intervals. Any RLV and NCD errors are stored during the 215 bit interval. The FM_NODE[0]_DV output is pulled low at the start of the 215 bit interval after errors are detected. Once low, FM_NODE[0]_DV remains in that state until an entire 215 bit interval has no RLV or NCD errors. At the start of the 215 bit interval subsequent to no RLV or NCD errors being detected, FM_NODE[0]_DV is pulled high. MODE_DV INPUT The active high Data Valid Mode input selects Fibre Channel data checking of the FM_NODE[0]± inputs. This is accomplished by having MODE_DV override the BYPASS[0]- control (see Figure 1), thereby forcing the data into the CDR to come from the FM_NODE[0]± inputs. The
MODE_DV pin is an LVTTL input and contains internal pull-up circuitry. To select Data Valid Mode, float MODE_DV high. Otherwise, MODE_DV should be connected to GND through a 1 k resistor. When MODE_DV is high, the user is able to use the BYPASS[0]- input to bypass invalid Fibre Channel data from the rest of the loop. For example, if FM_NODE[0]_DV is connected to the BYPASS[0]input, data from the CDR will only be routed to TO_NODE[1]± if the data has no RLV or NCD errors. If the DV block detects errors, the signal at TO_NODE[0]± will be routed to the TO_NODE[1]± outputs (see Figure 5). FM_NODE[0]_AV OUTPUT The Amplitude Valid (AV) block detects if the incoming data on FM_NODE[0]± is valid by examining the differential amplitude of that input. The incoming data is considered valid, and FM_NODE[0]_AV is driven high, as long as the amplitude is greater than 400 mV (differential peak-to-peak). FM_NODE[0]_AV is driven low as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100-400 mV (differential peak-to-peak), the FM_NODE[0]_AV output is undefined.
Table 1. Pin Connection Diagram to Achieve Desired CDR Location (see Figures 2, 3) Hard Disks Connection to PBC cells CDR position (x) Cell connected to Cable A 1 xA 0 A 0 Ax 1
x denotes CDR position with respect to hard disks.
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