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Details, datasheet, quote on part number:HDMP-0440
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Datasheet text preview:
Agilent HDMP-0440 Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops Data Sheet
Features · Supports 1.0625 GBd Fibre Channel operation · Supports 1.25 GBd Gigabit Ethernet (GE) operation · Quad PBC in one package · Equalizers on all inputs · High-speed LVPECL I/O · Buffered Line Logic (BLL) outputs (no external bias resistors required) · 0.5 W typical power at VCC = 3.3 V · 44 Pin, 10 mm, low-cost plastic QFP package Applications · RAID, JBOD, BTS cabinets · Two 2:1 muxes · Two 1:2 buffers · 1 N Gigabit serial buffer · N 1 Gigabit serial mux
Description The HDMP-0440 is a Quad Port Bypass Circuit (PBC), which provides a low-cost, low-power physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP-0440, hard disks may be pulled out or swapped while other disks in the array are available to the system. A PBC consists of multiple 2:1 multiplexers daisy chained together. Each port has two modes of operation: "disk in loop" and "disk bypassed." When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0440's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC's (e.g. an HDMP-1636A) Rx differential input pins. Data from the Disk Drive Transceiver IC's Tx differential outputs goes to the HDMP-0440's FM_NODE[n]± differential input pins. Figure 2
shows connection diagrams for disk drive array applications. When the "disk bypassed" mode is selected, the disk drive is either absent or non-functional and the loop bypasses the hard disk. The "disk bypassed" mode is enabled by pulling the BYPASS[n]- pin low. Leave BYPASS[n]- floating to enable the "disk in loop" mode. HDMP0440s may be cascaded with other members of the HDMP04XX/HDMP-05XX family through the appropriate FM_NODE[n] ± and TO_NODE[n] ± pins to accommodate any number of hard disks (see Figure 3). The unused cells in the HDMP-0440 may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells. An HDMP-0440 may also be configured as five 1:1 buffers, as two 2:1 multiplexers or as two 1:2 buffers.
HDMP-0440
CAUTION: As with all semiconductor ICs, it is advised that normal static precautionsb be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
HDMP-0440 Block Diagram BLL OUTPUT All TO_NODE[n]± high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL Outputs on the HDMP-0440 are of equal strength and can drive lengthy FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, unused outputs should have their differential pins shorted together with a short PCB trace. If longer traces or transmission lines are connected to the output pins, the lines should be differentially
terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance. EQU INPUT All FM_NODE[n]± high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs. The value of the termination resistor should match the PCB trace differential impedance. Alternatively, instead of a single resistor, two resistors in series, with an AC ground between them,
can be connected differentially across the FM_NODE[n]± inputs. The latter configuration attenuates high-frequency common mode noise. BYPASS[n]- INPUT The active low BYPASS[n]- inputs control the data flow through the HDMP-0440. All BYPASS pins are LVTTL and contain internal pullup circuitry. To bypass a port, the appropriate BYPASS[n]- pin should be connected to GND through a 1 k resistor. Otherwise, the BYPASS[n]- inputs should be left to float, as the internal pull-up circuitry will force them high.
FM_NODE[0]
FM_NODE[1]
FM_NODE[2]
FM_NODE[3]
FM_NODE[4]
TO_NODE[1]
TO_NODE[2]
TO_NODE[3]
TO_NODE[4]
EQU BLL
EQU
TTL BLL
EQU
TTL BLL
EQU
TTL BLL
EQU
TTL BLL
1 0
1 0
1 0
1 0
Figure 1. Block diagram of HDMP-0440.
2
TO_NODE[0]
BYPASS[2]
BYPASS[3]
BYPASS[1]
BYPASS[4]
HARD DISK A
HARD DISK B
HARD DISK C
HARD DISK D
FM_NODE[0] = FM_LOOP
SERDES
SERDES
SERDES
SERDES
EQU BLL
EQU
TTL BLL
EQU
TTL BLL
EQU
TTL BLL
EQU
TTL BLL
1
1 0
2
1 0
3
1 0
4
1 0
Figure 2. Connection diagram for disk array applications.
HARD DISK A FM_NODE[0] = FM_LOOP
HARD DISK B
HARD DISK C
HARD DISK D
HARD DISK H
HARD DISK E
TO_NODE[0] = TO_LOOP
FM_NODE[1]
FM_NODE[2]
FM_NODE[3]
BYPASS[2]
BYPASS[3]
FM_NODE[4]
TO_NODE[1]
TO_NODE[2]
TO_NODE[3]
TO_NODE[4]
BYPASS[1]
BYPASS[4]
HARD DISK F
HARD DISK G TO_NODE[0] = TO_LOOP
BLL
SERDES FM_NODE[1] TO_NODE[1] TO_NODE[2] BYPASS[1]
SERDES FM_NODE[2] TO_NODE[3] BYPASS[2]
SERDES FM_NODE[3] TO_NODE[4] BYPASS[3]
SERDES FM_NODE[4] FM_NODE[0] TO_NODE[0] TO_NODE[1] BYPASS[4]
SERDES FM_NODE[1] TO_NODE[2] BYPASS[1]
SERDES FM_NODE[2] TO_NODE[3] BYPASS[2]
SERDES FM_NODE[3] BYPASS[3] TO_NODE[4]
SERDES FM_NODE[4] BYPASS[4]
TTL
EQU BLL
EQU
TTL BLL
EQU
TTL BLL
EQU
TTL BLL
EQU
TTL BLL
EQU BLL
EQU
TTL BLL
EQU
TTL BLL
EQU
TTL BLL
EQU
1
1
1
1
1
1
1
1
1
0
2
0
3
0
4
0
1
0
2
0
3
0
4
0
Figure 3. Connection diagram for multiple HDMP-0440s.
I/O Type Definitions I/O Type I-LVTTL O-LVTTL HS_OUT HS_IN C S Definition LVTTL Input LVTTL Output High Speed Output, LVPECL compatible High Speed Input External Circuit Node Power Supply or Ground
3
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