|
Details, datasheet, quote on part number:HDMP-0450
| |
Datasheet text preview:
Agilent HDMP-0450 Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
Data Sheet
Description The HDMP-0450 is a Quad Port Bypass Circuit (PBC) which provides a low-cost, low-power physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP-0450, hard disks may be pulled out or swapped while other disks in the array are available to the system. A PBC consists of multiple 2:1 multiplexers daisy chained together. Each port has two modes of operation: "disk in loop" and "disk bypassed." When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0450's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC's (e.g., an HDMP-1636A) Rx differential input pins. Data from the Disk Drive Transceiver IC's Tx differential outputs goes to the HDMP-0450's FM_NODE[n] ± differential input
pins. Figure 2 shows connection diagrams for disk drive array applications. When the "disk bypassed" mode is selected, the disk drive is either absent or nonfunctional and the loop bypasses the hard disk. The "disk bypassed" mode is enabled by pulling the BYPASS[n]pin low. Leave BYPASS[n]floating to enable the "disk in loop" mode. HDMP-0450s may be cascaded with other members of the HDMP-04XX/HDMP-05XX family through the appropriate FM_NODE[n]± and TO_NODE[n]± pins to accommodate any number of hard disks (see Figure 3). The unused cells in the HDMP-0450 may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells. An HDMP-0450 may also be configured as five 1:1 buffers, as two 2:1 multiplexers, or as two 1:2 buffers.
Features · Supports 1.0625 GBd Fibre Channel operation · Supports 1.25 GBd Gigabit Ethernet (GE) operation · Quad PBC in one package · Signal detect on FM_NODE[0] input · Equalizers on all inputs · High speed LVPECL I/O · Buffered Line Logic (BLL) outputs (no external bias resistors required) · 0.5 W typical power at VCC = 3.3 V · 44 Pin, 10 mm, low-cost plastic QFP package Applications · RAID, JBOD, BTS cabinets · Two 2:1 muxes · Two 1:2 buffers · 1 => N gigabit serial buffer · N => 1 gigabit serial mux
HDMP-0450
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
FM_NODE[1]
FM_NODE[2]
FM_NODE[3]
FM_NODE[4]
TO_NODE[0]
BYPASS[2]
BYPASS[3]
BYPASS[4]
FM_NODE[0]
TO_NODE[1]
TO_NODE[2]
TO_NODE[3]
TO_NODE[4]
BYPASS[1]
BYPASS[0]
SD
EQU BLL TTL BLL EQU TTL BLL EQU TTL BLL EQU TTL BLL EQU TTL
TTL
SD
1 0
1 0
1 0
1 0
1 0
Figure 1. Block diagram of HDMP-0450.
HDMP-0450 Block Diagram BLL OUTPUT All TO_NODE[n]± high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL outputs on the HDMP-0450 are of equal strength and can drive in lengthy FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, unused outputs should have their differential pins shorted together with a short PCB trace. If longer traces or transmission lines are connected to the output pins, the lines should be differentially terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance.
EQU INPUT All FM_NODE[n]± high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs. The value of the termination resistor should match the PCB trace differential impedance. Alternativel y, instead of a single resistor, two resistors in series, with an AC ground between them, can be connected differentially across the FM_NODE[n]± inputs. The latter configuration attenuates high-frequency common mode noise. BYPASS[n]- INPUT The active low BYPASS[n]- inputs control the data flow through the HDMP-0450. All BYPASS pins are LVTTL and contain internal pullup circuitry. To bypass a port,
the appropriate BYPASS[n]- pin should be connected to GND through a 1 k resistor. Otherwise, the BYPASS[n]-inputs should be left to float, as the internal pull-up circuitry will force them high. SD OUTPUT The Signal Detect (SD) block detects if the incoming data on FM_NODE[0]± is valid by examining the differential amplitude of that input. The incoming data is considered valid, and SD is driven high, as long as the amplitude is greater than 400 mV (differential peak-topeak). SD is driven low as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100-400 mV (differential peak-to-peak), the SD output is undefined.
2
3
TO_NODE[1]
BLL
TO_NODE[1]
BLL
1
FM_NODE[1]
SERDES
EQU
1
HARD DISK A
BYPASS[1]
SERDES
HARD DISK A
0
TTL
1
FM_NODE[1]
EQU
TO_NODE[2]
BLL
BYPASS[1]
0
1
TTL
2
SERDES
FM_NODE[2] BYPASS[2]
EQU
HARD DISK B
0
TTL
1
BLL
TO_NODE[3]
TO_NODE[2]
BLL
3
SERDES
FM_NODE[3]
2
EQU
HARD DISK C
SERDES
EQU
BYPASS[3]
FM_NODE[2]
HARD DISK B
0
TTL
1
TO_NODE[4]
BYPASS[2]
0
1
BLL
TTL
4
SERDES
FM_NODE[4] BYPASS[4]
EQU
HARD DISK D
0
TTL
1
Figure 3. Connection diagram for multiple HDMP-0450s.
TO_NODE[3]
BLL
TO_NODE[0]
BLL
Figure 2. Connection diagram for Disk Array applications.
3
0
FM_NODE[0] = FM_LOOP
EQU
FM_NODE[3]
EQU
HARD DISK C
SERDES
BYPASS[0] = HIGH (FLOAT)
0
TTL
1
BYPASS[3]
0
1
TTL
TO_NODE[1] = TO_LOOP
BLL
1
FM_NODE[1] BYPASS[1] = HIGH (FLOAT)
EQU
TO_NODE[4]
BLL
0
TTL
1
4
TO_NODE[2]
FM_NODE[4]
EQU
BLL
SERDES
HARD DISK D
2
SERDES
FM_NODE[2] BYPASS[2]
EQU
HARD DISK E
BYPASS[4]
0
1
0
TTL
1
TTL
TO_NODE[3]
BLL
3
SERDES
FM_NODE[3] BYPASS[3]
TO_NODE[0] = TO_LOOP
BLL
EQU
HARD DISK F
0
TTL
1
0
FM_NODE[0] = FM_LOOP
EQU
TO_NODE[4]
BLL
4
SERDES
FM_NODE[4] BYPASS[4]
EQU
BYPASS[0] = HIGH (FLOAT)
0
1
HARD DISK G
TTL
0
TTL
1
TO_NODE[0]
BLL
SERDES
HARD DISK H
0
FM_NODE[0]
EQU
BYPASS[0]
0
TTL
1
|
|
