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Details, datasheet, quote on part number:HDMP-0452
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Agilent HDMP-0452 Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops
Data Sheet
Description The HDMP-0452 is a Quad Port Bypass Circuit (PBC) with a Clock and Data Recovery (CDR) circuit included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed". When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0452's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC's (e.g., an HDMP-1536A) Rx± differential input pins. Data from the Disk Drive
Transceiver IC's Tx± differential outputs goes to the HDMP-0452's FM_NODE[n]± differential input pins. Figures 3 and 4 show connection diagrams for disk drive array applications. When the "disk bypassed" mode is selected, the disk drive is either absent or nonfunctional and the loop bypasses the hard disk. The "disk bypassed" mode is enabled by pulling the BYPASS[n] pin low. Leave BYPASS[n] floating to enable the "disk in loop" mode. HDMP0452s may be cascaded with other members of the HDMP-04XX/ HDMP-05XX family through the FM_LOOP and TO_LOOP pins to accommodate any number of hard disks. See Table 2 to identify which of the 5 cells (0:4) will provide FM_LOOP and TO_LOOP pins (cable connections). The unused cells in this PBC may be bypassed by using pulldown resistors on the BYPASS[n] pins for these cells.
Features · Supports 1.0625 GBd fibre channel operation · Supports 1.25 GBd Gigabit Ethernet (GE) operation · Quad PBC/CDR in one package · CDR location determined by choice of cable input/output · Valid amplitude detection on FM_NODE[0] input · Equalizers on all inputs · High speed LVPECL I/O · Buffered Line Logic (BLL) outputs (no external bias resistors required) · 0.66 W typical power at VCC = 3.3 V · 44 pin, 10 mm, low cost plastic QFP package Applications · RAID, JBOD, BTS cabinets · 1 => 1-4 serial buffer with or w/o CDR
HDMP-0452
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by Electrostatic Discharge (ESD).
An HDMP-0452 may also be used as five 1:1 buffers, one with a CDR and four without. For example, an HDMP-0452 may be placed in front of a CMOS ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming signal (nonCDR path). In addition, the HDMP-0452 may be configured as two 2:1 multiplexers or as two 1:2 buffers. The HDMP-0452 design allows for CDR placement at any location with respect to the hard disk slots. For example, if the BYPASS[0] pin is floating and hard disk slots A to D are connected to PBC cells 1 to 4 respectively (see Figure 3), the CDR function will be performed before entering the hard disk at slot A. To obtain a CDR function after slot D (see Figure 4), BYPASS[1] must be floating and hard disk slots A to D must be connected to PBC cells 2,3,4, and 0 respectively. Table 2 shows all possible connections. For configurations where the CDR is before slot A, a Signal Detect (SD) pin shows the status of the signal at the incoming cable. HDMP-0452 Block Diagram
CDR
training controls. It does this by continually frequency locking onto the 106.25 MHz reference clock (REFCLK) and then phase locking onto the input data stream. Once bit locked, the CDR generates a high-speed sampling clock. This clock is used to sample or repeat the incoming data to produce the CDR output. The CDR jitter specifications listed in this data sheet assume an input that has been 8B/10B encoded.
SD OUTPUT
Unused outputs should not be left unconnected. Ideally, unused outputs should have their differential pins shorted together with a short PCB trace. If transmission lines are connected to the output pins, the lines should be differentially terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance.
EQU INPUT
The Signal Detect (SD) block detects if the incoming data on FM_NODE[0]± is valid by examining the differential amplitude of that input. The incoming data is considered valid, and SD is driven high, as long as the amplitude is greater than 400 mV (differential peak-to-peak). SD is driven low as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100-400 mV (differential peak-to-peak), SD is unpredictable.
BLL OUTPUT
All FM_NODE[n]± high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs.
BYPASS[N] INPUT
The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking feature allows the CDR to lock onto the input data stream without external
All TO_NODE[n]± high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL Outputs on the HDMP-0452 are of equal strength and can drive in excess of 120 inches of FR-4 PCB trace.
The active low BYPASS[n] inputs control the data flow through the HDMP-0452. All BYPASS pins are LVTTL and contain internal pull-up circuitry. To bypass a port, the appropriate BYPASS[n] pin should be connected to GND through a 1 k resistor. Otherwise, the BYPASS[n] inputs should be left to float. In this case, the internal pull-up circuitry will force them high.
REFCLK INPUT
The LVTTL REFCLK input provides a reference oscillator for frequency acquisition of the CDR. The REFCLK frequency should be within ± 100 ppm of one-tenth of the incoming data rate in baud (106.25 MHz ± 100 ppm for FC-AL running at 1.0625 GBd).
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FM_NODE[1]
FM_NODE[2]
FM_NODE[3]
FM_NODE[4]
TO_NODE[0]
B Y P A S S [ 2]
B Y P A S S [ 3]
B Y P A S S [ 4]
FM_NODE[0]
TO_NODE[1]
TO_NODE[2]
TO_NODE[3]
TO_NODE[4]
B Y P A S S [ 1]
B Y P A S S [ 0]
SD
EQU BLL TTL BLL EQU TTL BLL EQU TTL BLL EQU TTL BLL EQU TTL
SD
1 0
1 0
1 0
1 0
1 0
CDR
CPLL
TTL
REFCLK
Figure 1. Block diagram of HDMP-0452.
Table 1. Truth Table for CDR at Entry Configuration.
TO_LOOP FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] TO_NODE[4] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_NODE[3] TO_NODE[3] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] TO_NODE[2] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] TO_NODE[1] FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP BYPASS[4] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BYPASS[3] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BYPASS[2] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BYPASS[1] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Note: FM_LOOP = FM_NODE[0], TO_LOOP = TO_NODE[0], BYPASS[0] = 1.
Table 2. Pin Connection Diagram to Achieve Desired CDR Location (see Figures 3, 4). Hard Disks Connection to PBC Cells CDR Position (x) Cell Connected to Cable A BC D 1234 xA B C D 0 A BC D 0123 AxB C D 4 A BC D 4012 A BxC D 3 A BC D 3401 A B CxD 2 A BC D 2340 A B C Dx 1
Note: x denotes CDR position with respect to hard disks.
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