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Details, datasheet, quote on part number:HDMP-0480
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Datasheet text preview:
Agilent HDMP-0480 Octal Cell Port Bypass Circuit
without Clock and Data Recovery Data Sheet
Features · Supports 1.0625 GBd fibre channel operation · Supports 1.25 GBd gigabit Ethernet (GE) operation · Octal cell PBC in one package · Valid amplitude detection on FM_NODE[7] input · Equalizers on all inputs · High speed LVPECL I/O · Buffered Line Logic (BLL) outputs (no external bias resistors required) · 0.76 W typical power at Vcc=3.3V · 64 Pin, 10 mm, low cost plastic QFP package Applications · RAID, JBOD, BTS cabinets · Four 2:1 muxes · Four 1:2 buffers · 1 = > N gigabit serial buffer · N = > 1 gigabit serial mux
Description The HDMP-0480 is an Octal Cell Port Bypass Circuit (PBC). This device minimizes part count, cost and jitter accumulation. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk by-passed". When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0480's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC's (e.g. an HDMP-1636A) Rx± differential input pins. Data from the Disk Drive Transceiver IC's
Tx± differential outputs goes to the HDMP- 0480's FM_NODE[n]± differential input pins. When the "disk bypassed" mode is selected, the disk drive is either absent or non-functional and the loop bypasses the hard disk. The "disk bypassed" mode is enabled by pulling the BYPASS[n]pin low. Leave BYPASS[n]f loating to enable the "disk in loop" mode. HDMP-0480's may be cascaded with other members of the HDMP-04XX/HDMP-05XX family through the FM_NODE and TO_NODE pins to accommodate any number of hard disks. The unused cells in this PBC may be bypassed by using pulldown resist ors on the BYPASS[n]- pins for these cells. An HDMP-0480 may also be used as eight 1:1 buffers. In addition, an HDMP-0480 may be configured as four 2:1 multiplexers or as four 1:2 buffers.
HDMP-0480
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
1
BYPASS1
2
BYPASS2
3
BYPASS3
4
BYPASS4
5
BYPASS5
6
BYPASS6
7
BYPASS7
0
FM_NODE(7)_AV
AV
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
Figure 1. Block Diagram of HDMP-0480.
HDMP-0480 Block Diagram AV Output The Amplitude Valid (AV) block detects if the incoming data on FM_NODE[7]± is valid by examining the differential amplitude of that input. The incoming data is considered valid, and FM_NODE[7]_AV is driven high, as long as the amplitude is greater than 400 mV (differential peak-to-peak). FM_NODE[7]_AV is driven low as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100-400 mV (differential peak-to-peak), FM_NODE[7]_AV is unpredictable.
BLL Output All TO_NODE[n]± high-speed dif ferential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL Outputs on the HDMP-0480 are of equal strength and can drive in excess of 120 inches of FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, unused outputs should have their dif ferential pins shorted together with a short PCB trace. If transmission lines are connected to t he output pins, the lines should be differentially terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance.
EQU Input All FM_NODE[n]± high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs. BYPASS[N]- Input The active low BYPASS[n]- inputs control the data flow through the HDMP-0480. All BYPASS pins are LVTTL and contain internal pullup circuitry. To bypass a port, the appropriate BYPASS[n]- pin should be connected to GND through a 1k resistor. Otherwise, the BYPASS[n]- inputs should be left to float. In this case, the internal pull-up circuitry will force them high.
2
BYPASS0
FM_NODE[7]+
FM_NODE[6]+
FM_NODE[5]+
TO_NODE[7]+
TO_NODE[6]+
FM_NODE[7]-
FM_NODE[6]-
FM_NODE[5]-
TO_NODE[7]-
TO_NODE[6]-
BYPASS[6]-
BYPASS[7]GND GND GND VCC GND GND VCC GND GND GND GND BYPASS[0]FM_NODE[7]_AV FM_NODE[0]FM_NODE[0]+
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BYPASS[5]-
VCCHS
GND
GND
VCC
VCCHS TO_NODE[5]+ TO_NODE[5]VCCHS TO_NODE[4]+ TO_NODE[4]BYPASS[4]FM_NODE[4]+ FM_NODE[4]GND FM_NODE[3]+ FM_NODE[3]BYPASS[3]TO_NODE[3]+ TO_NODE[3]VCCHS
Agilent
HDMP-0480
nnnn-nnn Rz.zz S YYWW
Figure 2. HDMP-0480 Package Layout and Marking, Top View. nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision; S = Supplier Code; YYWW = Date Code (YY = year, WW = work week); COUNTRY = country of manufacture (on back side).
VCC
GND
TO_NODE[0]-
TO_NODE[0]+
VCCHS
TO_NODE[1]-
TO_NODE[1]+
BYPASS[1]-
FM_NODE[1]-
FM_NODE[1]+
VCC
FM_NODE[2]-
FM_NODE[2]+
BYPASS[2]-
TO_NODE[2]-
TO_NODE[2]+
I/O Type Definitions I/O Type
I-LVTTL O-LVTTL HS_OUT HS_IN C S
Definition
LVTTL Input LVTTL Output High Speed Output, LVPECL Compatible High Speed Input External circuit node Power supply or ground
3
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