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Details, datasheet, quote on part number:HDMP-0552
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| Part: | HDMP-0552 |
| Category: | Communication => Fiber Optics |
| Description: | 1.0625-2.125 GBD Quad Port Bypass Circuit With CDR And Data Valid Detection |
| Company: | Agilent Technologies, Inc. |
| Datasheet: | Download HDMP-0552 datasheet File size : 273 kB |
| Request For quote: | Find where to buy HDMP-0552
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Datasheet text preview:
Agilent HDMP-0552 Quad Port Bypass Circuit with CDR and Data Valid Detection
For Fibre Channel Arbitrated Loops
Data Sheet
Features · Supports 1.0625/2.125 GBd Fibre Channel operation · Quad PBC/CDR in one package · CDR location determined by choice of cable input/output · Amplitude valid detection on FM_NODE[0] input · Data valid detection on FM_NODE[0] input Run length violation detection Comma detection Configurable for both singleframe and multi-frame detection · Speed select pin for 1 or 2 GBd operation · Single REFCLK for 1 or 2 GBd operation · CDR selectable via external pin · Enable/disable equalizers on all inputs · Enable/disable selected highspeed output drivers · High speed LVPECL I/O · Buffered line logic (BLL) outputs (no external bias resistors required) · 1.1 W typical power at VCC = 3.3 V · Advanced 0.35 µ BiCMOS technology · 64 Pin, 10 mm, low cost plastic QFP package Applications · RAID, JBOD, BTS cabinets · 1=> 1-4 serial buffer with or without CDR
Description The HDMP-0552 is a Quad Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. See Figure 1 for block diagram. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A PBC consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed." When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the
HDMP-0552's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC (for example, an HDMP-263x) Rx± differential input pins. Data from the Disk Drive Transceiver IC Tx± differential output pins goes to HDMP-0552's FM_NODE[n]± differential input pins. Figure 2 and Figure 3 show connection diagrams for disk drive array applications. When the "disk bypassed" mode is selected, the disk drive is either absent or nonfunctional, and the loop bypasses the hard disk. Multiple HDMP-0552's may be cascaded or connected to other members of the HDMP-04xx family through the FM_LOOP and TO_LOOP pins to create loops for arrays of disk drives greater than 4. See Table 3 to identify which of the 5 cells (0:4) provides FM_LOOP, TO_LOOP pins (cell connected to cable).
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
Combinations of Quad PBCs can be utilized to accommodate any number of hard disks. The unused cells in a quad may be bypassed with pulldown resistors on the BYPASS[n]- pins for these cells. Additional power savings possible by turning off unused output drives. Please refer to BLL output section on page 3. An HDMP-0552 can be wired as a single or double mux cell with a CDR. It may also be used as a single or double mux cell without a CDR. All TO_NODE outputs of the HDMP-0552 are of equal strength. Therefore, this part may be used as a 1=>1- 4 buffer. The design of HDMP-0552 allows for placement of the CDR at any location with respect to hard disk slots. For example, if BYPASS[0]pin is tied to VCC and hard disk slots A to D are connected to PBC cells 1 to 4 in the same order, the CDR function is performed at entry to the HDMP-0552 (Figure 2). To achieve a CDR function at exit from the HDMP-0552, BYPASS[1]- must be tied to VCC and hard disk slots A to D must be connected to PBC cells 2, 3, 4, 0 in that order (Figure 3). Table 3 shows all possible connections. In case of CDR at entry, a Signal Detect (SD) pin shows the status of the signal at the incoming cable. The recommended method of setting the BYPASS[i]- pins HIGH is to drive them with a high-impedance signal. Internal pull-up resistors force the BYPASS[i]- pins to VCC. HDMP-0552 Block Diagram CDR The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking feature allows the CDR to lock onto the input data stream without external training controls. It does this by 2
continually frequency locking onto the reference clock (REFCLK) and then phase locking onto the input data stream. Once bit-locked, the CDR generates a high-speed sampling clock. This clock is used to sample or repeat the incoming data to produce the CDR output. The CDR jitter specifications listed in this data sheet assume an input that has been 8B/10B encoded. Data Valid Output The outgoing data from the CDR is checked for two types of errors. First, the data is checked for "Run Length Violations" (RLV), which are defined as a consecutive bit sequence greater than five. In addition, the data is checked for "No Comma Detected" (NCD), which is defined as no comma within a 215 bit frame. If neither of these errors occur, the data is considered valid Fibre Channel data, and FM_NODE[0]_DV is driven HIGH. For reporting errors, the data valid (DV) block contains a 215bit counter to provide a frame clock. All errors are reported relative to the rising edge of this internally generated clock. There are two LVTTL inputs for configuring the data validity checking. When MODE_DV is HIGH, the data input for the CDR comes from FM_NODE[0]. In this mode, the FM_NODE[0] input is checked for data validity. In addition, the FM_NODE[0]_DV LVTTL output can be used to drive BYPASS[0]- signal. In this configuration, when the data is invalid, the CDR output will be bypassed and the data from TO_NODE[0] will be passed on instead. When MODE_DV is LOW, the data validity checking is still taking place on output of the CDR; however, this data may be from another input besides FM_NODE[0]. In addition, the
CDR output data will always be passed on to TO_NODE[1] in this mode. Lastly, the LVTTL input FSEL selects single versus multi-frame operation of the DV block. For example, when FSEL is LOW, the FM_NODE[0]_DV output will be driven HIGH after 215 bits of good data. Similarly, FM_NODE[0]_DV will be driven LOW after one 215 bit sequence containing errors. This is "single frame" operation. When FSEL is HIGH, the DV block is operating in "multi-frame", or four frame, mode. In this mode, the FM_NODE[0]_DV will be driven HIGH only after four consecutive frames of valid data. Once HIGH, FM_NODE[0]_DV will only be driven LOW after four consecutive 215-bit frames containing errors. REFCLK Input and REF_RATE Control The LVTTL REFCLK input provides a reference oscillator for frequency acquisition of the CDR. The REFCLK frequency should be 53.125 Mhz or 106.25 Mhz +100 ppm. Set REF_RATE = 0 for a 53 Mhz and set REF_RATE = 1 for 106 MHz references. Either reference frequency can be used for both 1 GBd or 2 GBd rates. Amplitude Valid Output The Amplitude Valid (AV) block detects if the incoming data on FM_NODE[0]+ is valid by examining the differential amplitude of that input. The incoming data is considered valid and FM_NODE[0]_AV is driven HIGH, as long as the amplitude is greater than 200 mV (differential peak-to-peak). FM_NODE[0]_AV is driven LOW as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100 and 200 mV (differential peak-topeak), FM_NODE[0]_AV is unpredictable.
Equalizer Input All FM_NODE[n]+ high-speed differential inputs have an equalization setting to offset the effects of skin loss and dispersion on PCBs. This function is independently controllable for each input port using the EQ_SEL and NDx (x = 0-4) pins. The default setting for the equalization is TRUE. Equalization maybe set to FAULT for individual inputs by forcing EQ_SEL low and NDx (where x = port number) low for each port that the equalization setting is desired to be false. It is a logic OR function. For instance, forcing EQ_SEL, ND2 & ND3 pins low will turn off the equalization setting at FM_NODE[2]+ and FM_NODE[3]+ while the equalization setting will remain on for ports 0, 1 and 4.
FM_NODE [1] FM_NODE [2] BYPASS [1] BYPASS [2] TO_NODE [1] TO_NODE [2]
The EQ_SEL and NDx (x = 0-4) pins are LVTTL and contain internal pull-up circuitry. To force a pin low each pin should be connected to GND through a 1 kW resistor. Otherwise, these inputs should be left to float. In this case, the internal pull-up circuitry will force them high. BYPASS[n]- Input The active low BYPASS[n]- inputs control the data flow through the HDMP-0552. All BYPASS pins are LVTTL and contain internal pull-up circuitry. To bypass a port, the appropriate BYPASS[n]pin should be connected to GND through a 1 kW resistor. Otherwise, the BYPASS[n]inputs should be left to float. In this case, the internal pull-up circuitry will force them high.
FM_NODE [3] FM_NODE [4] BYPASS [3] BYPASS [4] TO_NODE [3] TO_NODE [4]
BLL Output All TO_NODE[n]+ high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination. Therefore, no external bias resistors are required. The BLL outputs on the HDMP-0552 are of equal strength. Unused outputs should be turned off independently. This reduces power and reduces the potential for crosstalk effects caused by incorrect terminations. If the unused outputs are not turned off they should be differentially terminated. The value of the termination resistor should match the PCB trace differential impedance. Each output port is set to active or inactive by the OUT_SEL and NDx (x = 0-4) pins.
FM_NODE [0]
EQU 1 0
EQU
EQU
EQU
EQU
TTL
TTL
TTL
BLL
BLL
BLL
BLL
TTL
1 0
1 0
1 0
1 0
0 0 1 1
CDR DV
CPLL
BLL
TO_NODE [0]
AV
TTL
SSTL
TTL
TTL
TTL
TTL
TTL
FM_NODE [0]_DV
BYPASS [0] -
CDR_RATE
MODE_DV
REF_RATE
CDR_SEL
REFCLK
F S EL
TTL
Figure 1 - Block Diagram of HDMP-0552
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FM_NODE [0]_AV
TTL
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