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Details, datasheet, quote on part number:HDMP-1022
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Datasheet text preview:
Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os Technical Data
HDMP-1022 Transmitter HDMP-1024 Receiver Features · Virtual Ribbon Cable · · · · · ·
Replacement On-Chip Encode / Decode On-Chip State Machine for Fully Automatic Link Management On-Chip Tx/Rx PLL Provides Frame Synchronization High Speed Serial Rate 150-1500 MBaud (User Selectable) Standard TTL Interface 16, 17, 20, or 21 Bits Wide Implemented in a Low Cost Aluminum M-Quad 80 Package
From the user's viewpoint, these products can be thought of as providing a "virtual ribbon cable" interface for the transmission of data. Parallel data (a frame) loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel, which can be either a coaxial copper cable or optical link, and is reconstructed into its original parallel form. The chip set hides from the user all the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. Unlike other links, the phaselocked-loop clock extraction circuit also transparently provides for frame synchronizationthe user is not troubled with the periodic insertion of frame synchronization words. In addition, the DC balance of the line code is automatically maintained by the chip set. Thus, the user can transmit arbitrary data without restriction. The Rx chip also includes a state-machine controller (SMC) that provides a startup handshake protocol for the duplex link configuration. The serial data rate of the Tx/Rx link is selectable in four ranges (see tables on page 5), and extends from 120 Mbits/s up to 1.25 Gbits/s. This translates into an encoded serial rate of 150-1500 MBaud. The parallel data interface is 16 or 20 bit TTL, pin selectable. A flag bit is available and can be used as an extra 17th or 21st bit under the user's control. The flag bit can also be used as an even or odd frame indicator for dual-frame transmission. If not used, the link performs expanded error detection. The serial link is synchronous, and both frame synchronization and bit synchronization are maintained. When data is not available to send, the link maintains synchronization by transmitting fill frames. Two (training) fill frames are reserved for handshaking during link startup. User control space is also supported. If Control Available (CAV) is asserted at the Tx chip, the least significant 14 or 18 bits of the data are sent and the Rx Control Available (CAV) line will indicate the data as a Control Word.
Applications · Backplane Serialization/ · · · ·
Bus Extender Video, Image Acquisition Point to Point Data Links Implement SCI-FI Standard Implement Serial HIPPI Specification
Description
The HDMP-1022 transmitter and the HDMP-1024 receiver are used to build a high-speed data link for point-to-point communication. The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package.
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Table of Contents
Topic .............. Page Typical Applications ...... 3 Setting the Operating Rate ........... 4 Transmitter Block Diagram .......... 6 Receiver Block Diagram ...... 8 Transmitter Timing Characteristics ..... 10 Receiver Timing Characteristics .......... 11 DC Electrical Specifications ....... 12 AC Electrical Specifications ....... 12 Typical Lock-Up Times .............. 12 Latency .............. 12 Absolute Maximum Ratings ........ 13 Thermal Characteristics ............. 13 I/O Type Definitions .... 13 Pin-Out Diagrams ....... 13 Transmitter Pin Definitions ........ 15 Receiver Pin Definitions ............. 19 Mechanical Dimensions and Package Information ....... 22 Recommended Handling Precautions .. 22 Appendix I: Additional Internal Architecture Information ........ 23 Line Code Description ...... 23 Data Frame Codes ...... 23 Control Frame Codes .. 24 Fill Frame Codes ......... 25 Tx Operation Principles ............. 26 Tx Encoding ...... 26 Tx Phase Locked Loop ...... 27 Rx Operation Principles ............. 28 Rx Encoding ...... 28 HDMP-1024 (Rx) Phase Locked Loop ......... 29 HDMP-1024 (Rx) Decoding ....... 29 HDMP-1024 (Rx) Link Control State Machine Operation Principle ..... 30 The State Machine Handshake Protocol ............. 30 Appendix II: Link Configuration Examples ......... 32 Duplex/Simplex Configurations ........... 32 Full Duplex ........ 32 Simplex Method I: Simplex with Low Speed Return Path .......... 33 Simplex Method II: Simplex with Periodic Sync Pulse ......... 33 Simplex Method III: Simplex with External Reference Oscillator........ 34 Data Interface for Single/Double Frame Mode .... 34 Single Frame Mode (MDFSEL=0)....... 35 Double Frame Mode (MDFSEL=1) ..... 35 Supply Bypassing and Integrator Capacitor ....... 36 Integrating Capacitor .. 37 Power Supply Bypassing and Grounding ............ 37 Electrical Connections ...... 38 I-TTL and O-TTL ......... 38 High Speed Interface: I-H50 & O-BLL ......... 38 Mode Options .... 39
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Typical Applications
The HDMP-1022/1024 chipset was designed for ease of use and flexibility. This allows the customer to tailor the use of this product, through the configuration of the link, based on his specific system requirements and application needs. Typical applications range from backplane serialization and bus extension to digital video transmission. Low latency bus extension of a 16 or 20 bit wide data bus may be achieved using the standard duplex configuration (see Figure 1d). In full duplex, the HDMP1022/1024 chipset handles all of the issues of link startup, maintenance, and simple error detection. If the bus width is 32 or 40 bits wide, the HDMP-1022/1024 chipset is capable of sending this data frame as two separate frame segments with the use of an external mux and demux as shown in Figure 1b. In this mode, called Double Frame Mode, the FLAG bit is used by the transmitter and receiver to indicate the first or second frame segment (Figure 19). The HDMP1022/1024 chipset in Double Frame Mode may also be configured in full duplex to achieve a 32/40 bit wide bus extension. For digital video transmission, simplex links are more common. The HDMP-1022/1024 chipset can transmit 16 to 20 bits of parallel data in standard or broadcast simplex mode (Figs. 1a, 1e). Additionally, 32 to 40 bit wide data can be transmitted over a single line (in Double Frame Mode) or two parallel lines, as in Figure 1c.
CLK Tx Rx CLK A) 16/20 BIT SIMPLEX TRANSMISSION
MUX CLK
Tx
Rx CLK
DEMUX
B) 32/40 BIT SIMPLEX TRANSMISSION
Tx CLK
Rx CLK
Tx CLK
Rx CLK
C) 32/40 BIT SIMPLEX TRANSMISSION WITH HIGH CLOCK RATES
Tx CLK
Rx CLK
Rx CLK
Tx CLK
D) 16/20 BIT DUPLEX TRANSMISSION
Tx CLK
Rx CLK
Rx CLK
Rx CLK E) SIMPLEX BROADCAST TRANSMISSION
Figure 1. Various Configurations Using the HDMP-1022/1024.
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