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Details, datasheet, quote on part number:QFCT-5281B
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Datasheet text preview:
Agilent HFCT-5205 SC Duplex Single Mode Transceiver
Data Sheet
Features · SC duplex single mode transceiver · Intermediate SONET OC3 SDH STM1 (S1.1) compliant · Single +5 V power supply · Multisourced 1 x 9 pin configuration · Aqueous washable plastic package · Interchangeable with LED multisourced 1 x 9 transceivers · Unconditionally eye safe laser IEC 825/CDRH Class 1 compliant · Two temperature ranges: 0°C to +70°C - HFCT-5205B/D -40°C to +85°C - HFCT-5205A/C Applications · SONET/SDH equipment interconnect · ATM 155 Mb/s links
Description The HFCT-5205 transceiver is a high performance, cost effective module for serial optical data communications applications specified for a signal rate of 155 MBd. It is designed to provide a SONET/SDH compliant link for 155 Mb/s intermediate reach links. This module is designed for single mode fiber and operates at a nominal wavelength of 1300 nm. It incorporates Agilent's high performance, reliable, long wavelength optical devices and proven circuit technology to give long life and consistent service.
The transmitter section uses a Multiple Quantum Well laser with full IEC 825 and CDRH Class I eye safety. The receiver section uses a planar PIN photodetector for low dark current and excellent responsivity. A pseudo-ECL logic interface simplifies interface to external circuitry.
Connection Diagram
RECEIVER SIGNAL GROUND o 1 RECEIVER DATA OUT o 2 RECEIVER DATA OUT BAR o 3 SIGNAL DETECT o 4 RECEIVER POWER SUPPLY o 5 TRANSMITTER POWER SUPPLY o 6 TRANSMITTER DATA IN BAR o 7 TRANSMITTER DATA IN o 8 TRANSMITTER SIGNAL GROUND o 9
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Top View
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Pin Descriptions: Pin 1 Receiver Signal Ground VEER: Directly connect this pin to the receiver ground plane. Pin 2 Receiver Data Out RD: See recommended circuit schematic, Figure 4. Pin 3 Receiver Data Out Bar RD: See recommended circuit schematic, Figure 4. Pin 4 Signal Detect SD: Normal optical input levels to the receiver result in a logic "1" output. Low optical input levels to the receiver result in a fault condition indicated by a logic "0" output. This Signal Detect output can be used to drive a PECL input on an upstream circuit, such as Signal Detect input or Loss of Signal-bar. Pin 5 Receiver Power Supply VCCR: Provide +5 V dc via the recommended transmitter power supply filter circuit. Locate the power supply filter circuit as close as possible to the VCC pin. Pin 6 Transmitter Power Supply VCCT: Provide +5 V dc via the recommended transmitter power supply filter circuit. Locate the power supply filter circuit as close as possible to the VCC pin. Pin 7 Transmitter Data In Bar TD: See recommended circuit schematic, Figure 4. Pin 8 Transmitter Data In TD: See recommended circuit schematic, Figure 4. Pin 9 Transmitter Signal Ground VEET: Directly connect this pin to the transmitter ground plane. Mounting Studs The mounting studs are provided for mechanical attachment to the circuit board. They are embedded in the nonconductive plastic housing and are not tied to the transceiver internal circuit and should be soldered into plated-through holes on the printed circuit board.
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Functional Description Receiver Section Design The receiver section contains an InGaAs/InP photo detector and a preamplifier within the receptacle, coupled to a postamp/decision circuit on a separate circuit board. The postamplifier is ac coupled to the preamplifier as illustrated in Figure 1. The coupling capacitor is large enough to pass the SONET/SDH test pattern at 155 MBd without significant distortion or performance penalty. If a lower signal rate, or a code which has significantly more low frequency content is used, sensitivity, jitter and pulse distortion could be degraded. Figure 1 also shows a filter network which limits the bandwidth of the preamp output signal. The filter is designed to bandlimit the preamp output noise and thus improve the receiver sensitivity.
These components will also reduce the sensitivity of the receiver as the signal bit rate is increased above 155 MBd. Noise Immunity The receiver includes internal circuit components to filter power supply noise. Under some conditions of EMI and power supply noise, external power supply filtering may be necessary. If receiver sensitivity is found to be degraded by power supply noise, the filter network illustrated in Figure 2 may be used to improve performance. The values of the filter components are general recommendations and may be changed to suit a particular system environment. Shielded inductors are recommended. Terminating the Outputs The PECL Data outputs of the receiver may be terminated with the standard Thevenin-equivalent 50 ohm to VCC - 2 V termination. Other standard PECL terminating techniques may be used.
The two outputs of the receiver should be terminated with identical load circuits to avoid unnecessarily large ac current in VCC. If the outputs are loaded identically the ac current is largely nulled. The Signal Detect output of the receiver is PECL logic and must be loaded if it is to be used. The Signal Detect circuit is much slower than the data path, so the ac noise generated by an asymmetrical load is negligible. Power consumption may be reduced by using a higher than normal load impedance for the Signal Detect output. Transmission line effects are not generally a problem as the switching rate is slow. The Signal Detect Circuit The Signal Detect circuit works by sensing the peak level of the received signal and comparing this level to a reference.
TRANSIMPEDANCE PREAMPLIFIER RECEIVER RECEPTACLE
FILTER LIMITING AMPLIFIER
DATA OUT PECL OUTPUT BUFFER
DATA OUT
GND
SIGNAL DETECT CIRCUIT
PECL OUTPUT BUFFER
SD
Figure 1 - Receiver Block Diagram
3.3 µH VCC 100 nF 100 nF
FILTERED VCC to DATA LINK + 10 µF
Figure 2 - p Filter Network for Noise Filtering
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