|Category||Analog & Mixed-Signal Processing|
|Company||AKM Semiconductor, Inc.|
|Datasheet||Download AK4309B datasheet
General Description The a 1bit stereo DAC for multimedia audio systems. A 1bit DAC can achieve monotonicity and low distortion with no adjustment and is superior to traditional R-2R ladder based DACs. In the AK4309B, the loss of accuracy from clock jitter is also improved by using SCF techniques for on-chip post filter. The AK4309B includes continuous time filter with single end output and does not need any external parts. The master clock can be either or 384fs, supporting various audio environment. Features
Sampling Rate Ranging from 50kHz On chip Perfect filtering 8 times FIR Interpolator 2nd order SCF and CTF Total Response: 20kHz On chip Buffer with Single End Output Master Clock: or 384fs High Tolerance to Clock Jitter TTL Level Digital Interface THD+N: -84dB Dynamic Range: 90dB Output Level: 3.4Vpp Power Supply: 5V±10% Low Power Dissipation: at 5V Small Package: 20pin SSOP Pin Compatible with AK4310/4309AParameter Power Supply Digital I/F level DR Output Voltage Click Noise Function of Pin 4 Package
PIN/FUNCTION No. Pin Name TST1 DVDD DVSS NC I/O I Function Test Pin (Pull-down pin) Must be left floating or tied to DVSS. Digital Power Supply Pin Digital Ground Pin No Connection Reset Pin When at "L", the is in power-down mode and is held in reset. The AK4309B should always be reset upon power-up. Master Clock Input Pin An external TTL clock should be input on this pin. The fs is selected by CKS pin. Master Clock Select Pin "L": MCLK=256fs, "H": MCLK=384fs Serial Bit Input Clock Pin This clock is used to latch SDATA. Serial Data Input Pin 2's complement MSB-first data is input on this pin. L/R Clock Pin This input determines which channel is currently being input on the Serial Data Input pin, SDATA. "H": Lch, "L": Rch analog output pin Lch analog output pin Common Voltage pin, AVDD/2 Normally connected to AVSS with a 0.1uF ceramic capacitor in parallel with a 10uF electrolytic cap. Analog Power Supply Pin Analog Ground Pin No Connection "H" Voltage Reference Input Pin The differential Voltage between VREFH and VREFL inputs set the analog output range. The VREFH pin is normally connected to AVDD and the VREFL pin is connected to AVSS. A 0.1uF ceramic capacitor should be as near to both pins. "L" Voltage Reference Input Pin Zero Input Detect Pin When SDATA of both channels follow a total 8192 LRCK cycles with "0" input data, this pin goes "H".
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