|Category||Data Conversion => DAC (Digital to Analog Converters)|
|Company||AKM Semiconductor, Inc.|
|Datasheet||Download AK4317 datasheet
The a 1bit stereo DAC with channel separated volume and channel mixer. This DAC also includes 18bit digital filter and analog LPF. A 1bit DAC can achieve monotonicity and low distortion with no adjustment and is superior to traditional R-2R ladder based DACs. In the AK4317, the loss of accuracy from clock jitter is also improved by using SCF techniques for on-chip post filter. Therefore, the AK4317 is suitable for the system like STB including PLL circuit.Features
Sampling Rate Ranging from 50kHz On chip Perfect filtering 8 times FIR Interpolator 2nd order SCF 2nd order CTF Digital de-emphasis for 44.1, 48kHz sampling L/R Separated Volume L/R Mixing Soft Mute Audio I/F format : MSB justified, LSB justified, I2S Master Clock: or 384fs High Tolerance to Clock Jitter THD+N: -86dB DR: 92dB Power to 5.5V Small Package: 24pin VSOP AK4311 CompatibleOrdering Guide AK4317-VF AKD4317 Pin Layout -40+85°C Evaluation Board 24pin VSOP(0.65mm pitch)
Parameter Resolution Operating Temperature Power Supply Digital I/F level X'tal Oscillator DR Package -4085°C 35.5V CMOS Yes 92dB SSOP -1070°C 35.5V CMOS Yes 91dB SSOP -4085°C 4.55.5V TTL No 92dB VSOP
2. Pin Compatibility The following pin functions are changed from AK4311/A. But when X'tal oscillating circuit is not used, it is possible to change to AK4317 without changing the board layout.
Power-Down Mode Pin When at "L", the is in power-down mode and is held in reset. The AK4317 should always be reset upon power-up. Digital Input Format Pin Master Clock Input Pin Digital Input Format Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin 2's complement MSB-first data is input on this pin. L/R Clock Pin Control Data Input Pin Must be tied to "H" or "L" if this pin is not used. Control Clock Pin Must be tied to "H" or "L" if this pin is not used. Chip Select Pin Must be tied to "H" if this pin is not used. Test Pin Must be left floating. Soft Mute Pin When this pin goes "H", soft mute cycle is initiated. When returning "L", the output mute releases. De-emphasis Enable Pin (Internal Pull-down pin) Master Clock Select Pin MCLK=256fs,"H": MCLK=384fs Channel 1 analog output pin Channel 0 analog output pin Common Voltage Pin, AVDD/2 Normally connected to AVSS with a 0.1uF ceramic capacitor in parallel with a 10uF electrolytic cap. Analog Power Supply Pin Analog Ground pin Voltage Reference Input Pin The differential Voltage between this pin and AVSS set the analog output range. Normally connected to AVSS with a 0.1uF ceramic capacitor. Zero Input Detect Pin Test Pin Must be left floating or tied to AVSS. (Internal Pull-down pin) (Internal Pull-down pin)DIF0 MCLK DIF1 BICK SDATA LRCK CDATA CCLK CS TST2 SMUTE
Note: All input pins except pull-down pins should not be left floating.
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