Details, datasheet, quote on part number: AK5352-VF
PartAK5352-VF
Category
Description
CompanyAKM Semiconductor, Inc.
DatasheetDownload AK5352-VF datasheet
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Features, Applications

GENERAL DESCRIPTION The 20-bit, 96kHz sampling rate for DAT and DVD, 64x oversampling rate(64fs), 2-channel A/D converter for stereo digital systems. The modulator in the AK5352 uses the new developed Enhanced Dual bit architecture. This new architecture achieves the wider dynamic range, while keeping much the same superior distortion characteristics as the conventional Single bit way. The AK5352 is available in a small 24pin VSOP package which will reduce your system space. FEATURES

Sampling Rate to 96kHz Full-differential inputs S/(N+D): 97dB DR, S/N: 104dB Linear phase digital filter Pass band: 0 22kHz(@fs=48kHz) Pass band ripple: 0.005dB Stop band attenuation: 80dB Digital HPF for DC-offset cancel Master clock: 256fs/384fs Power supply: 5V5% Small package: 24pinVSOP

PIN/FUNCTION No. 2 3 Pin Name AINR+ AINRVREF I/O I O FUNCTION Right channel analog positive input pin Right channel analog negative input pin Voltage Reference output pin (VA-2.6V) Normally connected to VA with a 0.1uF ceramic capacitor in parallel with a 10uF electrolytic capacitor. Analog section Analog Power Supply, +5V Analog section Analog Ground Left channel analog positive input pin Left channel analog negative input pin Test pin (Pull-down pin) Should be left floating.

High Pass Filter Enable pin (Pull-up pin) "H": ON "L": OFF Digital section Digital Power Supply pin, +5V Digital section Digital Ground pin Power Down pin "L" brings the device into power-down mode. Must be done once after power-on. Master Clock input pin CMODE="H" : 384fs CMODE="L" : 256fs Serial Data Clock pin Data is clocked out at the falling edge of SCLK. Slave mode: 64fs clock is input usually. Master mode: SCLK outputs a 64fs clock. SCLK stays low during the power-down mode(PD="L"). L/R Channel Clock Select pin Slave mode: An fs clock is fed to this LRCK pin. Master mode: LRCK output an fs clock. LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset when SMODE1 "H". Frame Synchronization Signal pin Slave mode: When "H", data bits are clocked out on SDATA. I S slave mode ignores FSYNC, it should hold "L" or "H". Master mode: FSYNC outputs 2fs clock. Stay low during the power-down mode(PD="L").


 

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