Details, datasheet, quote on part number: AK7712A-VT
CompanyAKM Semiconductor, Inc.
DatasheetDownload AK7712A-VT datasheet
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Features, Applications

The is a DSP(Digital Signal Processor) with built-in high performance 20bit 2ch ADC and 4ch DAC, on purposeto control the sound field. It is possible to calculate 383 steps on 44.1kHz and 48kHz sampling respectively. In case of 32kHz sampling, it can caluculate to 511 steps. With a combination of this LSI and external memory for delay data,it can berealized easily to control the sound field such as Echo, Surround Presence Controller, and Key-control which are needed forsomething like Karaoke. Parametric Equalizing can be done without external memory.


[ DSP unit ] Word length: 24-bit (data RAM) Instruction cycle time: 54ns(maximum speed) Multiplier: 16 40-bit Divider: 16 16-bit Program RAM: 32 bit External memory: DRAM,Pseudo-SRAM and SRAM can be connected (only use for delay data). Sampling frequency: 32kHz48kHz Automatic clear function of external RAM: 47msec after bringing RST high at fs=48kHz (include internal data RAM) Microcomputer interface: synchronized signal type 8-bit serial input 1 channel, synchronized signal type 24-bit serial output 1 channel Master clock: 512(511)/384(383)/256(255)fs The value inside ) is maximum calculation steps. 512fs mode is available when 32kHz sampling is chosen. Conversion of master/slave mode for LRCK and BCLK: When master mode is selected, the outputs of LRCK and BCLK depend on the set-up for input format. Serial input ports(2~4ch), and output : 16/20/24 bit words [ ADC unit 64 Oversampling ADC: 2ch 92dB S/(N+D): 98dB DR, S/N: [ DAC unit 128 Oversampling DAC: 4ch 86dB S/(N+D): 97dB DR, S/N: Digital HPF (fc=1Hz) [ Total ] Power supply: 100pin LQFP(0.5mm pitch) Package:

40-bit(fixed-point, 2 instruction cycle time) 16-bit(fixed-point, 17 instruction cycle time) 34-bit arithmetic operation 24-bit arithmetic logic operationShift: 1-,2-,3-,4-,6-,8-,15-bit right/left shift AK7712A has indirect shift function. (A shift using DBUS data can not use DBUS as multiplication input.)Register: 4(ACC) [for ALU] 8(TMP) [for DBUS connection]Double precision operation: 24-bit(data)31-bit(coefficient), Internal MemoryProgram RAM: 384 word 32-bitData RAM: 128 word 24-bitCoefficient RAM: 256 word 16-bitOffset RAM: 40 word 16-bit (for external memory access)Microcomputer buffer: 16 word 16-bit 3) External Memory Access (SRAMPseudo-SRAMDRAM)Objective memory: 1 / SRAM 1 / Pseudo-SRAM 1 / DRAM (Half volume of 1M DRAM is used as 512k memory.)Treating bit length: (24-bit is available, but double time is needed for access.)The number of times to access: SRAM, 256k Pseudo-SRAM 384fs : DRAM, 1M Pseudo-SRAM (32 at one DRAM) : SRAM, 256k Pseudo-SRAM 256fs : DRAM, 1M Pseudo-SRAM (21 at one DRAM)Memory access time: less than 100nsecMaximum address length: 65535 sampling times (at 1M SRAM) 48kHz 4) Input/Output PortInput: 2ch analog input: 20-bit ADC, at BCLK=32fs) [when built-in ADC is connected.]...MSB first serial input 2ch digital input: MSB justified at BCLK=32fs) [when built-in ADC is isolated.]

2ch digital input: MSB justified 16-24-bit / LSB justified 16-24-bit 4ch analog output: 20-bit DAC, at BCLK=32fs) [when built-in ADC is connected.] 4ch digital output: MSB justified at BCLK=32fs) [when built-in ADC is isolated.]

...MSB first serial output 2ch digital output: MSB justified 16-24-bit/ LSB justified 16-bit 5) Cascade connection with this LSI is possible. 6) Interface to Microcomputer: synchronized 8-bit serial input / synchronized 24-bit serial output 7) Calculation Cycle: max 18.432MHz(54nsec) [at 5V] 8) Master/Slave conversion of LRCK BCLK is possible. 9) BCLK: 32fs/48fs/64fs (64fs only at master mode)

AK7712A Block Diagram 1) ADC,DAC Inside Connection Mode (OPCL: L)
Note: Please use SDIN2,SDDA and SDDA2 with "L" or open. SDAD,SDOUT2 and SDOUT3 output "L".


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