Details, datasheet, quote on part number: AK9813AF
PartAK9813AF
CategoryMultimedia
Description12ch 8bit D/A Converter With EePROM
CompanyAKM Semiconductor, Inc.
DatasheetDownload AK9813AF datasheet
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Features, Applications

General Description The AK9813A includes 12 channel, 8bit D/A converters with on-chip output buffer amps and it is capable to store the input digital data of each DAC by on-chip non-volatile CMOS EEPROM. The AK9813A is optimally designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for replacing mechanical trimmers.

Features

EEPROM SECTION 12 words 4 organization for DAC D/A converter section 12 channels Resolution : 8bit DNL : -1a+2 LSB INL : 1.5 LSB Analog Output Voltage Range : GND a VCC Operating Voltage Range Digital section : 2.7Va5.5V Analog section 5.0V0.5V,3.3V0.3V 24pin VSOP

Serial Data Input Pin SEL=High : 16bit data input format SEL=Low : 14bit data input format (SEL=High:CS I/F) AK9813A reads out the data with LSB first in the 16bit shift register to DO pin synchronously with falling edge of CLK. When the CS pin is high level, the DO pin becomes high impedance. In STATUS mode, the DO pin outputs Ready/Busy status. (SEL=Low:LD I/F) AK9813A reads out the data with MSB first in the 14bit shift register to DO pin synchronously with falling edge of CLK. In WRITE mode, the DO pin outputs Ready/Busy status. Shift Clock Input Pin(Schmitt-trigger input) AK9813A takes in the data from DI pin synchronously with rising edge of the CLK pin. The data are transferred to the internal shift register. Chip Select Input Pin(Schmitt-trigger input) The CS/LD is internally pulled up to VCC. (SEL=High:CS I/F) After the CS pin changes from high level to low level while the CLK pin is high level, the AK9813A can input the data to the internal shift register and takes in the data from the DI pin synchronously with the rising edge of the CLK pin. After the CS pin changes from high level to low level while the CLK pin is low level, the AK9813A becomes the status mode and reads out the Ready/Busy status to the DO pin. When the CS pin changes from low level to high level regardless of Low/High level of the CLK pin, the AK9813A removes from the status mode to the normal mode. The CS pin usually should be kept at high level. (SEL=Low:LD I/F) When the LD pin receives high pulse, the data of the internal shift register is transferred to the internal decoder or the register for D/A. The LD pin usually should be kept at low level.


 

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