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Details, datasheet, quote on part number:3933
 
 
Part:3933
Category:Power Management => Motor Controller/Drivers => DC Motor drivers/Controllers => DC Motor Drivers
Description:Three-phase Power MOSFET Controller
Company:Allegro Micro Systems, Inc.
Datasheet:Download 3933 datasheet   File size : 173 kB
Request For quote:  Find where to buy 3933
 



Datasheet text preview:
Data Sheet 26301.100

3933
RESET PGND AGND GLC DEAD REF SC

THREE-PHASE POWER MOSFET CONTROLLER
The A3933SEQ is a three-phase MOSFET controller for use with bipolar brushless dc motors. It drives all n-channel external power FETs, allowing system cost savings and minimizing r(DS)on power loss. The high-side drive block is implemented with bootstrap capacitors at each output to provide the floating positive supply for the gate drive. The high-side circuitry also employs a unique "intelligent" FET monitoring circuit that ensures the gate voltages are at the proper levels before turn-on and during the ON cycle. This device is targeted for applications with motor supplies from 12 V to 28 V. Internal fixed off-time PWM current-control circuitry can be used to regulate the maximum load current to a desired value. The peak loadcurrent limit is set by the user's selection of an input reference voltage and external sensing resistor. The fixed off-time pulse duration is set by a user-selected external RC timing network. A power-loss braking circuit brakes the motor on an under-voltage condition. The device is configured to either coast or dynamically brake the motor when this occurs.
Dwg. PP-068

32

31

30

3

4

2

1

GHC CC GLB SB GHB CB GLA SA GHA

5 6 7 8

29 28 27 26

SENSE RC PWM BRKSEL BRKCAP BRAKE DIR H2 H3

BRAKE

9 10 11 12 13

25 24

CONTROL LOGIC

23 19 22 21

14

17

FAULT 18

VBB 19

LCAP 16

VCCOUT

FAULT

MODE

CA

H1 20

15

The A3933SEQ is supplied in a 32-lead rectangular (9 x 7) plastic chip carrier (quad pack) for minimum-area, surface-mount applications.

ABSOLUTE MAXIMUM RATINGS at TA = 25°C
Supply Voltage, VBB ..... 28 V (peak) .... 30 V Terminal Voltage, VCCOUT ........ 13.2 V (peak) .... 15 V Logic Input Voltage Range, VIN ......... -0.3 V to VLCAP + 0.3 V Sense Voltage Range, VSENSE ..... -5 V to VLCAP Output Voltage Range, VSA, VSB, VSC ......... -5 V to +30 V VGHA, VGHB, VGHC . -5 V to VBB + 14 V VCA, VCB, VCC ............ VSX + 14 V Operating Temperature Range, TA ......... -20°C to +85°C Junction Temperature, TJ ........ +150°C Storage Temperature Range, TS ....... -55°C to +150°C

FEATURES AND BENEFITS
I I I I I I I I I I I I I I Drives External N-Channel FETs Intelligent High-Side Gate Drive Selectable Coast or Dynamic Brake on Power Down Adjustable Dead Time for Cross-Conduction Protection Selectable Fast or Slow Current-Decay Modes Internal PWM Peak Current Control Reset/Coast Input 120° Hall Commutation with Internal Pullup Internal 5-V Regulator Low-Side Synchronous Rectification Direction Control PWM Speed-Control Input Fault-Diagnostic Output Under-Voltage Protection

3933 THREE-PHASE POWER MOSFET CONTROLLER
Functional Block Diagram

+V

CONNECT FOR 12-V OPERATION VCCOUT

LCAP

VBB

REGULATOR UNDERVOLTAGE DETECT BOOTSTRAP MONITOR BOOTSTRAP CHARGE CX C boot GHX

H1 H2 H3 CONTROL LOGIC

TURN-ON DELAY

HIGH-SIDE DRIVER

DIR RESET MODE PWM RC RT CT REF SENSE
TO VCCOUT

GATE-SOURCE MONITOR
1 OF 3 HIGH-SIDE DRIVERS

SX

TO 1 OF 3 MOTOR PHASES TO LCAP

RC BLANKING
(FIXED OFF TIME)

LOW-SIDE SYNCHRONOUS RECTIFICATION

DEAD-TIME ADJUST

DEAD

+ ­ TURN-ON DELAY
1 OF 3 LOW-SIDE DRIVERS
LOW-SIDE DRIVER

GLX

BRAKE BRKSEL BRKCAP BRAKE

PGND

RS

BOOTSTRAP LOW VGS LOW INVALID HALL UNDERVOLTAGE

FAULT AGND TO SENSE
Dwg. FP-045

RECOMMENDED OPERATING CONDITIONS
Supply Voltage, VBB ..... 15 V to 28 V or, if VBB = VCCOUT .. 12 V ±10% Logic Input Voltage Range, VIN ..... -0.3 V to +4.8 V Sense Voltage Range, VSENSE ...... -1 V to +1 V RC Resistance ......... 10 k to 100 k PWM Frequency, fPWM ..... 20 kHz to 100 kHz
Dwg. OA-007-32

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1999, Allegro MicroSystems, Inc.

3933 THREE-PHASE POWER MOSFET CONTROLLER

ELECTRICAL SPECIFICATIONS at TA = 25°C, VBB = VCCOUT = 12 V, Cload = 1000 pF, Cboot = 0.047 µF (unless noted otherwise). Limits Parameter Supply Current
Quiescent Current Reference Voltage Ref. Volt. Load Regulation Output Voltage Output Voltage Regulation

Symbol
I BB V LCAP

Conditions
RESET low, fPWM = 40 kHz RESET high

Min
­ ­ 4.75 ­ 10.8 ­ 2.0 ­

Typ
16 15 5.0 10 12 ­ ­ ­ <1.0 ­ 10.5 ­ 10.5 ­ 50 40 100 100 3000 180

Max
19 17 5.25 25 13.2 25 ­ 0.8 10 -130 11.5 0.30 11.5 0.25 ­ ­ ­ ­ ­ ­

Units
mA mA V mV V mV V V µA µA V V V V ns ns ns ns ns ns

VLCAP(ILCAP) ILCAP = 0 to -2 mA V CCOUT VBB = 28 V VCCOUT(ICCOUT) VBB = 28 V, ICCOUT = 0 to -10 mA VIH VIL I IH I IL V IH = 2 V VIL = 0.8 V

Digital Logic Levels
Logic Input Voltage Logic Input Current

­ -70 9.5

Gate Drive
Low-Side Output Voltage High-Side Output Voltage Low-Side Output Switching Time High-Side Output Switching Time DEAD Time (Source OFF to Sink ON) V GLxH V GLxL V GHxH V GHxL trGLx t fGLx trGHx t fGHx tDEAD IGHx = 1 mA 1 V to 8 V 8 V to 1 V 1 V to 8 V 8 V to 1 V IDEAD = 10 µA IDEAD = 215 µA IGLx = 1 mA ­ 9.0 ­ ­ ­ ­ ­ ­ ­

Continued -- NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.

www.allegromicro.com

3933 THREE-PHASE POWER MOSFET CONTROLLER

ELECTRICAL SPECIFICATIONS at TA = 25°C, VBB = VCCOUT = 12 V, Cload = 0.001 µF, Cboot = 0.047 µF (unless noted otherwise), continued. Limits Parameter Bootstrap Capacitor
Bootstrap Charge Current Bootstrap Output Voltage Leakage Current

Symbol
I Cx V Cx I Cx V io I SENSE I RC V RCL V RCH f PWM UVLO V CxSx V GHxSx V FAULT IBRKCAP V GLxH

Conditions

Min
50

Typ
100 10.5 15 0 ­ 945 1.1 3.0 ­ 10.2 ­ ­ 6.3 ­ 30 6.6

Max
150 11.5 20 ± 5.0 -1.0 1040 1.2 3.2 100 10.7 10.35 ­ ­ 0.8 ­ ­

Units
mA V µA mV µA µA V V kHz V V V V V µA V

Reference Sx High side switched high, Sx = VBB

9.5 ­ ­ ­ 850 1.0 2.7

Current Limit
Offset Voltage Input bias current RC Charge Current RC Voltage Threshold PWM frequency Range

Operating I n c r e a s i n g V BB D e c r e a s i n g VBB VBB = 12 V IO = 1 mA VBB = 8 V, BRKSEL 2 V VBB = 0, BRKCAP = 8 V

20 9.7 9.35 9.5 ­ ­ ­ ­

Protection Circuitry
Undervoltage Threshold Boot-Strap Capacitor Volt. High-Side Gate-Source Volt. Fault Output Voltage

Brake Function
Brake Cap. Supply Current Low-Side Gate Voltage

NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

3933 THREE-PHASE POWER MOSFET CONTROLLER
Terminal Descriptions
Terminal
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Name
PGND RESET GLC SC GHC CC GLB SB GHB CB GLA SA GHA CA V CCOUT LCAP FAULT MODE V BB H1 H3 H2 DIR BRAKE BRKCAP BRKSEL PWM RC SENSE REF DEAD AGND

RESET -- A logic input used to enable the device, internally pulled up to VLCAP (+5 V). A logic HIGH will disable the device and force all gate drivers to 0 V, coasting the motor. A logic LOW allows the gate drive to follow commutation logic. This input overrides BRAKE. GLA/GLB/GLC -- Low-side, gate-drive outputs for external NMOS drivers. External series-gate resistors (as close as possible to the NMOS gate) can be used to control the slew rate seen at the power-driver gate, thereby controlling the di/dt and dv/dt of the SA/SB/SC outputs. Each output is designed and specified to drive a 1000 pF load with a rise time of 50 ns. SA/SB/SC -- Directly connected to the motor, these terminals sense the voltages switched across the load. These terminals are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drive. GHA/GHB/GHC -- High-side, gate-drive outputs for external NMOS drivers. External series-gate resistors (as close as possible to the NMOS gate) can be used to control the slew rate seen at the power-driver gate, thereby controlling the di/dt and dv/dt of the SA/SB/SC outputs. Each output is designed and specified to drive a 1000 pF load with a rise time of 100 ns. CA/CB/CC -- High-side connections for the bootstrap capacitors, positive supply for high-side gate drive. The bootstrap capacitor is charged to approximately VCCOUT when the associated output SA/SB/SC terminal is low. When the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage needed for n-channel power FETs.
continued next page

www.allegromicro.com