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Details, datasheet, quote on part number:3936
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Datasheet text preview:
3936
PRELIMINARY DATASHEET - 8/29/2002 (Subject to change without notice)
DMOS THREE PHASE PWM MOTOR DRIVER
Designed for Pulse Width Modulated (PWM) current control of three phase brushless DC motors, the A3936SED is capable of peak output currents to ± 3A and operating voltages to 50 V. Internal fixed off-time PWM current control timing circuitry can be configured to operate in slow, fast and mixed decay modes. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, and crossover current protection. Special power up sequencing is not required. The A3936 is supplied in a 44-lead plastic PLCC with a copper batwing tab (suffix `ED'). The power tab is at ground potential and needs no electrical isolation.
ABSOLUT E MAXIMUM RAT INGS at T A = +25°C
Load Supply Voltage, VBB ....... 50 V Output Current, IOUT ......... ± 3 A* Logic Supply Voltage, VDD ...... 7.0 V Logic Input Voltage Range, VIN ........... -0.3 V to VDD + 0.3 V (tW<30ns) ....... -1.0V to VDD +1V Sense Voltage, VSENSE........ 0.5 V Reference Voltage, VREF ...... VDD Package Power Dissipation (TA = +25°C), PD A3936SED .... 32°C/W Operating Temperature Range, TA....... -20°C to +85°C Junction Temperature, TJ ..... +150°C Storage Temperature Range, TS ..... -55°C to +150°C
* Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C.
Features
ÿ ÿ ÿ ÿ ÿ ÿ ÿ ±3A, 50 V Continuous Output Rating Low RDS(ON) Outputs, typically 500 mohm source, 315 mOhm sink Configurable Mixed, Fast and Slow Current Decay Modes Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection Tachometer Output for External Speed Control Loop
3936 Three Phase PWM Motor Driver
FUNCTIONAL BLOCK DIAGRAM
.22uf/50V .22uf/100V VREG CP2 CP1
V DD
REGULAT OR
CHARGE PUMP VCP .22uf/50V VBB1 VBB2 OUT A OUT B OUT C LSS2 LSS1 SENSE .1uF ZERO CURRENT DETECT RS GND BUFFER/ DIVIDER RE F
TACH HBIAS
BANDGAP
OVERVOLT AGE UNDERVOLT AGE AND FAULT DET ECT
HAHA+ HALL HBHB+ HALL HCHC+ HALL Control Logi c Comm Logi c
VREG
VCP
GATE DRIVE
SLEEP DIR EXTMODE BRAKE SR ENABLE
VDD OSC CURRENT SENSE
BLANK PFD1 PFD2
PW M T IMER
+
-
+ -
3936 Three Phase PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TJ = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50KHz (unless noted otherwise) Lim its Characteristics Output Drivers
Load Supply Voltage Range VBB Operating During Sleep Mode Output Leakage Current IDSS VOUT = VBB VOUT = 0 V Output On Resistance RDSON Source Driver, IOUT = -3A Sink Driver, IOUT = 3A Body Diode Forward Voltage VF Source Diode, IF = -3A Sink Diode, IF = 3A Motor Supply Current IBB fPW M < 50 kHz Charge Pump On, Outputs Disabled Sleep Mode Logic Supply Current IDD fPW M < 50 kHz Outputs Off Sleep Mode (Inputs below .5V) 9 0 4 2 <1.0 <1.0 50 50 20 -20 .55 .35 1.4 1.3 7 5 20 10 8 100 V V µA µA V V mA mA uA mA mA µA
Sym bol
Test Conditions
M in.
Typ.
M ax.
Units
Control Logic
Logic Supply Voltage Range Logic Input Voltage VDD VIN(1) VIN(0) Logic Input Current (except ENABLE) Logic Input Current ENABLE Input Internal Oscillator IIN(1) IIN(0) IIN(1) IIN(0) fOSC VIN = VDD*.5 VIN = VDD*.2 VIN = VDD*.5 VIN = VDD*.2 OSC shorted to GND ROSC= 51K Operating 3 VDD*.5 -20 -20 3 3.4 4 4 5.0 <1.0 <-1.0 5.5 VDD*.2 20 20 100 30 5 4.6 V V V µA µA µA µA MHz MHz
3936 Three Phase PWM Motor Driver
ELECT RICAL CHARACT ERIST ICS at T J = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50KHz (unless noted otherwise)
Lim its Characteristics Sym bol Test Conditions M in. Typ. M ax. Units
Control Logic
Buffer Input Offset Volt. VREF Input Voltage Range Reference Input Current Comparator Input Offset Volt. GM Error IREF VIO VERR (Note 3) Propagation Delay Times tpd VI O Operating VREF = VDD ,VBB=0 to 50V VREF = 0 V VREF = VDD VREF = .5V 50% TO 90%, SR Enabled PW M CHANGE TO SOURCE ON PW M CHANGE TO SOURCE OFF PW M CHANGE TO SINK ON PW M CHANGE TO SINK OFF Crossover Delay tCOD SR Enabled 600 50 600 50 300 750 150 750 100 600 1000 350 1000 150 1000 ns ns ns ns ns -4 -14 0.0 -.5 ±10 0 ±5 4 14 VDD 0.5 mV V µA mV % %
Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis
TJ TJ Rising VDD
2.45 0.05
165 15 2.7 0.10
2.95
°C °C V V
NOTES: 1. 2. 3.
Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device pin.
VERR =((VREF/10) VSENSE)/(VREF/10)
3936 Three Phase PWM Motor Driver
ELECT RICAL CHARACT ERIST ICS at T A = +25°C, VBB = 50 V, VDD = 5.0 V fPWM < 50KHz (unless noted otherwise)
Lim its Characteristics Sym bol Test Conditions M in. Typ. M ax. Units
Hall Logic
Hall Input Current Common Mode Input Range AC Input Voltage Range Hysteresis Pulse Reject Filter IHALL VCMR VHALL VHYS TA= -20 to 85 deg C. VIN = 1.2V -1 .3 .120 10 3 5.5 30 8 0 1 2.5 µA V Vp-p mV µs
Hall Bias Output Sat Voltage
VHB IHB
IOUT=40mA, TA= -20 to 85 deg C.
.4
.5 40
V mA
Tach Output
VOL
IOUT= 500uA
.5
V
NOTES: 1. 2.
Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device pin.
Commutation Truth Table
120 spacing HB HC + + + + + + + + + + + + + + + + + + + + + Outputs OUTB OUTC LO Z Z LO HI LO HI Z Z HI LO HI HI Z Z HI LO HI LO Z Z LO HI LO Z Z Z Z
HA
1 2 3 4 5 6 1 2 3 4 5 6
DIR FOR FOR FOR FOR FOR FOR REV REV REV REV REV REV X X
OUTA HI HI Z LO LO Z LO LO Z HI HI Z Z Z
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