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Part: 5800AND5801
Category:
Description:
Company: Allegro Micro Systems, Inc.
Datasheet: Download 5800AND5801 datasheet File size : 115 kB
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5800 AND 5801
UCN5800L
1 14
BiMOS II LATCHED DRIVERS
The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data (`D' type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power outputs are bipolar npn Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or microprocessor I/O. The UCN5800A and UCN5800L each contain four latched drivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eight latched drivers. The UCN5800A/L and UCN5801A/EP/LW supersede the original BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These second-generation devices are capable of much higher data input rates and will typically operate at better than 5 MHz with a 5 V logic supply. Circuit operation at 12 V affords substantial improvement over the 5 MHz figure. The CMOS inputs are compatible with standard CMOS and NMOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/power loads: relays, lamps, solenoids, small dc motors, etc. All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 500 mA and will withstand at least 50 V in the OFF state. Because of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. The UCN5800A is furnished in a standard 14-pin DIP; the UCN5800L and UCN5801LW in surface-mountable SOICs; the UCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; the UCN5801EP in a 28-lead PLCC.
Data Sheet 26180.10B*
UCN5800A
CLEAR STROBE IN 1 IN 2 IN 3 IN 4 GROUND 1 2 3 4 5 6 7 14 VDD 13 12 OUTPUT ENABLE SUPPLY OUT 1 OUT 2 OUT 3 OUT 4 COMMON
LATCHES
11 10 9 8
Dwg. PP-014A
Note the UCN5800A (DIP) and the UCN5800L (SOIC) are electrically identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, VCE . . . . . . . . . . . . . . 50 V Supply Voltage, VDD . . . . . . . . . . . . . . 15 V Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Continuous Collector Current, lC . . . . . . . . . . . . . . . . . . . . . . 500 mA Package Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature Range, TS . . . . . . . . . . . . . . . -55°C to +150°C
Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges.
FEATURES
s To 4.4 MHz Data Input Rate s High-Voltage, High-Current Outputs s Output Transient Protection s CMOS, NMOS, s Internal Pull-Down Resistors TTL Compatible Inputs s Low-Power CMOS Latches s Automotive Capable
Always order by complete part number, e.g., UCN5801EP .
5800 AND 5801 BiMOS II LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
SUPPLY VDD COMMON
IN N OUT N STROBE
CLEAR GROUND OUTPUT ENABLE
COMMON MOS CONTROL
TYPICAL MOS LATCH
TYPICAL BIPOLAR DRIVE
Dwg. FP-016-1
TYPICAL INPUT CIRCUIT
VDD
2.5
22-PIN DIP, RJA = 56°C/W
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
28-LEAD PLCC, RJA = 68°C/W 14-PIN DIP, RJA = 73°C/W
2.0
IN
24-LEAD SOIC, RJA = 85°C/W
1.5
1.0
Dwg. EP-010-4A
0.5
14-LEAD SOIC, RJA = 120°C/W
0
25
50
75
100
125
150
AMBIENT TEMPERATURE IN ° C
Dwg. GP-023-1A
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1985, 2002 Allegro MicroSystems, Inc.
5800 AND 5801
BiMOS II LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Characteristic Output Leakage Current Symbol ICEX Test Conditions VCE = 50 V, TA = +25°C VCE = 50 V, TA = +70°C Collector-Emitter Saturation Voltage VCE(SAT) IC = 100 mA IC = 200 mA IC = 350 mA, VDD = 7.0 V Input Voltage VIN(0) VIN(1) VDD = 12 V VDD = 10 V VDD = 5.0 V (See Note) Input Resistance rI N VDD = 12 V VDD = 10 V VDD = 5.0 V Supply Current I DD(ON) (Each Stage) ID D ( O F F ) (Total) Clamp Diode Leakage Current Clamp Diode Forward Voltage IR VDD = 12 V, Outputs Open VDD = 10 V, Outputs Open VDD = 5.0 V, Outputs Open VDD = 12 V, Outputs Open, Inputs = 0 V VDD = 5.0 V, Outputs Open, Inputs = 0 V VR = 50 V, TA = +25°C VR = 50 V, TA = +70°C VF IF = 350 mA Min. -- -- -- -- -- -- 10.5 8.5 3.5 50 50 50 -- -- -- -- -- -- -- -- Typ. -- -- 0.9 1.1 1.3 -- -- -- -- 200 300 600 1.0 0.9 0.7 -- 50 -- -- 1.7 Limits Max. 50 100 1.1 1.3 1.6 1.0 -- -- -- -- -- -- 2.0 1.7 1.0 200 100 50 100 2.0 Units µA µA V V V V V V V k k k mA mA mA µA µA µA µA V
NOTE: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic "1".
STROBE 28 OUTPUT ENABLE 27 SUPPLY V DD CLEAR
ST
NC
OE
C
NC
NC
26
4
3
2
1
IN1 IN 2
5 6 7
LATCHES
25 24 23 22
OUT1 OUT 2 OUT 3 OUT4
UCN5801EP
(additional pinout diagrams are on next page)
IN 3 IN 4 IN 5
8 9
21 OUT 5 20 19 OUT 6 OUT7
IN 6 10 IN 7 11
14 NC 13 NC 17 NC K 15 16
12
LAMP DIODE COMMON
GROUND
OUT8
IN 8
18
Dwg. PP-037
5800 AND 5801 BiMOS II LATCHED DRIVERS
UCN5801A
CLEAR STROBE IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 GROUND 1 2 3 4 5 6 7 8 9 10 11
LATCHES
CLEAR F
22 VDD 21 20 19 18 17 16 15 14 13 12
OUTPUT ENABLE SUPPLY
STROBE A OUTPUT ENABLE C B C B A C B
OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 COMMON
G
G
INN D OUTN E E
Dwg. No. A-10,895A
TIMING CONDITIONS
(Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Strobe Enabled (Data Set-Up Time) .......... 50 ns B. Minimum Data Active Time After Strobe Disabled (Data Hold Time) ..... 50 ns C. Minimum Strobe Pulse Width ........ 125 ns
Dwg. PP-015
D. Typical Time Between Strobe Activation and Output On to Off Transition ........... 500 ns E. Minimum Time Between Strobe Activation and Output Off to On Transition ........... 500 ns
UCN5801LW
CLEAR STROBE IN1 IN 2 IN 3 IN 4 IN5 IN 6 IN 7 IN 8 GROUND NO CONNECTION 1 2 3 4 5 6 7 8 9 10 11 12 NC NC
LATCHES
F. Minimum Clear Pulse Width .... 300 ns
24 VDD 23 22 21 20 19 18 17 16 15 14 13 OUTPUT ENABLE SUPPLY OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 COMMON NO CONNECTION
Dwg. PP-015-1
G. Minimum Data Pulse Width ..... 225 ns Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output OFF condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs to the OFF condition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches.
TRUTH TABLE
OUTPUT
I NN 0 1 X X X X STROBE 1 1 X X 0 0 CLEAR 0 0 1 X 0 0 ENABLE 0 0 X 1 0 0 t-1 X X X X ON OFF OUTN t OFF ON OFF OFF ON OFF
X = irrelevant. t-1 = previous output state. t = present output state.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5800 AND 5801
BiMOS II LATCHED DRIVERS
TYPICAL APPLICATION
UNIPOLAR STEPPER-MOTOR DRIVE
+30 V
OUTPUT ENABLE (ACTIVE LOW) CLEAR 1 STROBE IN 1 µ IN 2 IN 3 IN 4 2 3
LATCHES
14 VDD 13 12 11 10 9 8 VDD OUT 1 OUT 2 OUT 3 OUT 4
4 5 6 7
UCN-5800A
+30 V
Dwg. No. B-1537
UNIPOLAR WAVE DRIVE
UNIPOLAR 2-PHASE DRIVE
STROBE IN 1 IN 2 IN 3 IN 4 OUT 1 OUT 2 OUT 3 OUT 4
STROBE IN 1 IN 2 IN 3 IN 4 OUT 1 OUT 2 OUT 3 OUT 4
Dwg. GP-060
Dwg. GP-060-1
Others parts begin by 58
58-1 58-2
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