|
|
Part: 5810-F
Category:
Power Management
Description: Bimos ii 10-bit Serial-input, Latched Source Drivers With Active-dmos Pull-downs
Company: Allegro Micro Systems, Inc.
Datasheet: Download 5810-F datasheet File size : 115 kB
Request For quote: Find where to buy 5810-F
Datasheet text preview:
5810 -F
UCN5810AF
OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4 1 2 3 LATCHES 4 5 6 7 8 9 VDD ST CLK REGISTER REGISTER LATCHES BLNK 13 12 11 10 BLANKING OUT 1 OUT 2 OUT 3 VBB 15 14 18 17 16 OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN
BiMOS II 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
The UCN5810AF, UCN5810EPF, and UCN5810LWF combine a 10-bit CMOS shift register and accompanying data latches, control circuitry, bipolar sourcing outputs with DMOS active pull-downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The UCN5810AF/EPF/LWF feature reduced supply requirements (active DMOS pull-downs) and lower saturation voltages when compared with the original UCN5810A. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. Similar devices are available as the UCN5811A (12 bits), UCN5812AF/EPF (20 bits), and UCN5818AF/EPF (32 bits). The UCN5810AF/EPF/LWF output source drivers are NPN Darlingtons capable of sourcing up to 40 mA. The DMOS active pull-downs are capable of sinking up to 15 mA. For inter-digit blanking, all of the output drivers can be disabled and the DMOS sink drivers turned on by the BLANKING input high. The UCN5810AF is furnished in an 18-pin dual in-line plastic package. The UCN5810EPF is furnished in a 20-lead plastic chip carrier. The UCN5810LWF is furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and lower output saturation voltages allow all devices to source 25 mA from all outputs continuously, over the entire operating temperature range. All devices are also available for operation between -40°C and +85°C. To order, change the prefix from `UCN' to `UCQ'.
Data Sheet 26182.24C
Dwg. PP-029
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ............ 15 V Driver Supply Voltage, VBB ........... 60 V Continuous Output Current Range, IOUT .. -40 mA to +15 mA Input Voltage Range, VIN ...... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD (UCN5810AF) ... 2.27 W* (UCN5810EPF) ...... 1.78 W* (UCN5810LWF) ...... 1.56 W* Operating Temperature Range, TA .......... -20°C to +85°C Storage Temperature Range, TS ........ -55°C to +150°C
*Derate linearly to 0 W at +150°C.
FEATURES
I High-Speed Source Drivers I 60 V Minimum Output Breakdown I Improved Replacements for TL4810B I Low Output Saturation Voltages I Low-Power CMOS Logic and Latches I To 3.3 MHz Data Input Rate I Active DMOS Pull-Downs
Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges.
Note that the UCN5810AF (dual in-line package) and UCN5810LWF (small-outline IC package) are electrically identical and share a common pin number assignment.
Always order by complete part number, e.g., UCN5810AF .
5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
UCN5810EPF
20 19 OUT10 OUT 6
FUNCTIONAL BLOCK DIAGRAM
CLOCK V DD LOGIC SUPPLY SERIAL DATA OUT
3
2
1
CLOCK NC GROUND LOGIC SUPPLY STROBE
4 5 6 7 8
CLK LATCHES REGISTER
18 V BB 17 16
SERIAL DATA OUT LOAD SUPPLY NC SERIAL DATA IN BLANKING
SERIAL DATA IN STROBE
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V DD ST
REGISTER 15 LATCHES BLNK 14
BLANKING MOS BIPOLAR
12
10
11
13
9
OUT 5
OUT1
V BB
Dwg. PP-059
LOAD SUPPLY
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
UCN5810LWF
OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4 1 2 3 LATCHES 4 5 6 7 8 9 VDD ST CLK REGISTER REGISTER LATCHES BLNK 13 12 11 10 BLANKING OUT 1 VBB 15 14 18 17 16 OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN
TYPICAL INPUT CIRCUIT
VDD
IN
OUT 2 OUT 3
Dwg. PP-029-1
Dwg. PP-029-1
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
SUFFIX 'EP', R JA = 59°C/W
Dwg. EP-010-4A
2.0
SUFFIX 'A', R JA = 60°C/W
TYPICAL OUTPUT DRIVER
V BB
1.5
1.0
0.5
SUFFIX 'LW', R JA = 80°C/W
OUT N
0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150
Dwg. GP-024B
Dwg. GP-024A
Dwg. No. A-14,219
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1988, 2000 Allegro MicroSystems, Inc.
5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V unless otherwise noted.
L i m i t s @ VD D = 5 V Characteristic Output Leakage Current Output Voltage Symbol IC E X V OUT(1) V OUT(0) Test Conditions VOUT = 0 V, TA = +70°C IOUT = -25 mA IOUT = 1 mA IOUT = 2 mA Output Pull-Down Current I OUT(0) VOUT = 5 V to VBB VOUT = 20 V to VBB Input Voltage VIN(1) VIN(0) Input Current I IN(1) IIN(0) Serial Data Output Voltage V OUT(1) V OUT(0) Maximum Clock Frequency Supply Current f clk I DD(1) I DD(0) IB B ( 1 ) IB B ( 0 ) Blanking to Output Delay tP H L tP L H Output Fall Time Output Rise Time tf tr All Outputs High All Outputs Low Outputs High, No Load Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% CL = 30 pF, 90% to 10% CL = 30 pF, 10% to 90% VIN = VDD VIN = 0.8 V IOUT = -200 µA IOUT = 200 µA Mln. -- 58 -- -- 2.0 -- 3.5 -0.3 -- -- 4.5 -- 3.3* -- -- -- -- -- -- -- -- Typ. -5.0 58.5 1.0 -- 3.5 -- -- -- -- -0.05 4.7 200 -- 100 100 0.7 10 2000 1000 1450 650 Max. -15 -- 1.5 -- -- -- 5.3 +0.8 100 -0.5 -- 250 -- 300 300 2.0 100 -- -- -- -- Limits @ VDD = 12 V Min. -- 58 -- -- -- 8.0 10.5 -0.3 -- -- 11.7 -- -- -- -- -- -- -- -- -- -- Typ. -5.0 58.5 -- 1.0 -- 13 -- -- -- -0.1 11.8 100 -- 200 200 0.7 10 1000 850 650 700 Max. -15 -- -- 1.5 -- -- 12.3 +0.8 240 -1.0 -- 200 -- 500 500 2.0 100 -- -- -- -- Units µA V V V mA mA V V µA µA V mV MHz µA µA mA µA ns ns ns ns
Negative current is defined as coming out of (sourcing) the specified device pin. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
CLOCK DATA IN C STROBE BLANKING G OUTN
Dwg. No. A-12,649A
A
B
D
E
F
Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) ........ 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ........... 75 ns C. Minimum Data Pulse Width ....... 150 ns D. Minimum Clock Pulse Width ...... 150 ns E. Minimum Time Between Clock Activation and Strobe ..... 300 ns F. Minimum Strobe Pulse Width .... 100 ns G. Typical Time Between Strobe Activation and Output Transistion ....... 500 ns Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.
TRUTH TABLE
Serial Shift Register Contents Data Clock I n p u t I n p u t I1 I2 I3 . . . IN-1 I N H L X H L R 1 R 2 ... R 1 R 2 ... R N-2 R N-1 R N-2 R N-1 R N-1 R N X X Serial Data Strobe Output Input R N-1 R N-1 RN X PN L H R 1 R 2 R 3 ... P1 P2 P3 ... X
L = Low Logic Level H = High Logic Level X = Irrelevant
Latch Contents I1 I2 I3 ... IN-1 I N Blanklng
Output Contents I1 I2 I3 . . . I N - 1 I N
R 1 R 2 R 3 ... X X X ...
R N-1 R N PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L
P1 P2 P3 ...
PN-1 PN
X
X
...
P = Present State
R = Previous State
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
UCN5810AF
Dimensions in Inches (controlling dimensions)
18 10 0.014 0.008
0.430 0.280 0.240
MAX
0.300
BSC
1
0.070 0.045
0.100 0.920 0.880
BSC
9
0.005
MIN
0.210
MAX
0.015
MIN
0.150 0.115 0.022 0.014
Dwg. MA-001-18A in
Dimensions in Millimeters (for reference only)
10 0.355 0.204
18
10.92 7.11 6.10
MAX
7.62
BSC
1
1.77 1.15
2.54 23.37 22.35
BSC
9
0.13
MIN
5.33
MAX
0.39
MIN
3.81 2.93 0.558 0.356
Dwg. MA-001-18A mm
NOTES: 1. 2. 3. 4.
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 21 devices.
www.allegromicro.com
Others parts begin by 58
58-1 58-2
|
|
|
