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Part: 5815
Category:
Description:
Company: Allegro Micro Systems, Inc.
Datasheet: Download 5815 datasheet File size : 115 kB
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5815
UCN5815A
ENABLE STROBE IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 GROUND 1 2 3 4 5 6 7 8 9 10 11
LATCHES
BiMOS II 8-BIT LATCHED SOURCE DRIVERS
Designed primarily for use with high-voltage vacuum-fluorescent displays, the UCN5815A and UCN5815EP BiMOS II integrated circuits consist of eight npn Darlington source drivers with output pulldown resistors, a CMOS latch for each driver, and common STROBE, BLANKING, and ENABLE functions. BiMOS II devices have considerably better data-input rates than the original BiMOS circuits. With a 5 V logic supply, they will operate to at least 4.4 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs cause minimum loading and are compatible with standard CMOS and NMOS logic commonly found in microprocessor designs. TTL circuits may require the use of appropriate pull-up resistors. The bipolar outputs may be used as segment, dot (matrix), bar, or digit drivers in vacuum-fluorescent displays. All eight outputs can be activated simultaneously at ambient temperatures in excess of 75°C. To simplify printed wiring board layout, output connections are opposite the inputs. A minimum component display subsystem, requiring few or no discrete components, can be assembled using the UCN5815A/EP with the UCN5810AF/EPF/LWF, UCN5812AF/EPF, or UCN5818AF/EPF serial-to-parallel latched drivers. Suffix `A' devices are furnished in a standard 22-pin plastic DIP; suffix `EP' indicates a 28-lead PLCC.
Data Sheet 26183.10A*
22 VDD 21 20 19 18 17 16 15 14 13 VBB 12
BLANKING LOGIC SUPPLY OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 LOAD SUPPLY
Dwg. PP-015-3
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, VOUT . . . . . . . . . . . . . . 60 V Logic Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . 4.5 V to 15 V Load Supply Voltage Range, VBB . . . . . . . . . . . . . . . . . . 5.0 V to 60 V Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Continuous Output Current, IOUT . . . . . . . . . . . . . . . . . . . . . . -40 mA Package Power Dissipation, PD (UCN5815A) . . . . . . . . . . . . . . . 2.5 W* (UCN5815EP) . . . . . . . . . . . . . 2.27 W* Operating Temperature Range, TA . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature Range, TS . . . . . . . . . . . . . . . . -55°C to +150°C * Derate linearly to 0 W at +150°C. Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges.
FEATURES
I I I I I I To 4.4 MHz Date-lnput Rate High-Voltage Source Outputs CMOS, NMOS, TTL Compatible Inputs Low-Power CMOS Latches Internal Pull-Down Resistors Wide Supply-Voltage Range
Always order by complete part number: Part Number UCN5815A UCN5815EP Package 2 2 - Pin DIP 28-Lead PLCC
5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V, VDD = 5 V and 12 V (unless otherwise noted).
Characteristic Output Off Voltage Output On Voltage Output Pull-Down Current Output Leakage Current Input Voltage Symbol VO U T VOUT I OUT I OUT V IN(1) IOUT = -25 mA, VBB = 60 V VOUT = VBB TA = 70°C VDD = 5.0 V VDD = 12 V V IN(0) Input Current II N ( 1 ) VDD = VIN = 5.0 V VDD = VIN = 12 V Input lmpedance Supply Current Z IN lB B VDD = 5.0 V All outputs on, All outputs open All outputs off, All outputs open lDD VDD = 5.0 V, All outputs off, All inputs = 0 V VDD = 12 V, All outputs off, All inputs = 0 V VDD = 5.0 V, One output on, All inputs = 0 V VDD = 12 V, One output on, All inputs = 0 V NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin. Test Conditions Min. -- 57.5 400 -- 3.5 10.5 -0.3 -- -- 50 -- -- -- -- -- -- Limits Max. 1.0 -- 850 -15 5.3 12.3 +0.8 100 240 -- 10.5 100 100 200 1.0 3.0 Units V V µA µA V V V µA µA k mA µA µA µA mA mA
TYPICAL INPUT CIRCUIT
VDD
TYPICAL OUTPUT DRIVER
V BB
IN
100 K
OUT
Dwg. No. EP-010-4A
Dwg. No. EP-021-3
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1984, 2000 Allegro MicroSystems, Inc.
5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS
UCN5815EP
Dwg. No. A-10,991
TIMING CONDITIONS
(VDD = 5 V, TA = +25°C, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Strobe Enabled (Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns B. Minimum Data Active Time After Strobe Disabled (Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns C. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ns D. Typical Time Between Strobe Activation and Output ON to OFF Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 µs E. Typical Time Between Strobe Activation and Output OFF to ON Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns F. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns Timing is representative of a 4.4 MHz data input rate. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.
Dwg. No. A-14,357
Information present at an input is transferred to its latch when the STROBE and ENABLE are high. The latches will continue to accept new data as long as both STROBE and ENABLE are held high. With either STROBE or ENABLE in the low state, no information can be loaded into the latches. When the BLANKING input is high, all of the output buffers are disabled (off) without affecting the information stored in the latches. With the BLANKING input low, the outputs are controlled by the state of the latches.
TRUTH TABLE
INPUTS IN N 0 1 X X X X X STROBE 1 1 X 0 0 X X ENABLE 1 1 X X X 0 0 BLANK 0 0 1 0 0 0 0 OUTN T-1 X X X 1 0 1 0 T 0 1 0 1 0 1 0
X = irrelevant T-1 = previous output state T = present output state
5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS
UCN5815A
Dimensions in Inches (cvontrolling dimensions)
22 12 0.015 0.008
0.500 0.380 0.330
MAX
0.400
BSC
1
2 0.070 0.030
3 1.120 1.050
11 0.100
BSC
0.005
MIN
0.210
MAX
0.015
MIN
0.160 0.115 0.022 0.014
Dwg. MA-002-22 in
Dimensions in Millimeters (for reference only)
22 12 0.381 0.204
12.70 9.65 8.39
MAX
10.16
BSC
1
2 0.070 0.030
3 28.44 26.67
2.54
BSC
11
0.13
MIN
5.33
MAX
0.39
MIN
4.06 2.93 0.558 0.356
Dwg. MA-002-22 mm
NOTES: 1. 2. 3. 4.
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 17 devices.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5815 BiMOS II 8-BIT LATCHED SOURCE DRIVERS
UCN5815EP
Dimensions in Inches (controlling dimensions
18 12
0.013 0.021 0.219 0.191
19
11
0.026 0.032 0.456 0.450
BSC
INDEX AREA
0.050 0.219 0.191
0.495 0.485 25 5
26 0.020
MIN
28
1
4
0.165 0.180
0.456 0.450 0.495 0.485
Dwg. MA-005-28A in
Dimensions in Millimeters (for reference only)
18 12
0.331 0.533 5.56 4.85
19
11
1.27
BSC
0.812 0.661 11.58 11.43 12.57 12.32
INDEX AREA
5.56 4.85
25
5
26 0.51
MIN
28
1
4
4.57 4.20
11.582 11.430 12.57 12.32
Dwg. MA-005-28A mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 38 devices or add "TR" to part number for tape and reel.
Others parts begin by 58
58-1 58-2
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