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Part: 5818
Category:
Description:
Company: Allegro Micro Systems, Inc.
Datasheet: Download 5818 datasheet File size : 119 kB
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Datasheet text preview:
5818 -F
UCN5818EPF
SERIAL DATA OUT LOAD SUPPLY LOGIC SUPPLY SERIAL DATA IN OUT30 OUT31 OUT32 OUT 1 OUT 2 NC OUT3
BiMOS II 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
Designed primarily for use with vacuum-fluorescent displays, the UCN5818AF and UCN5818EPF smart power BiMOS II drivers combine CMOS shift registers, data latches, and control circuitry, with bipolar highspeed sourcing outputs and DMOS active pull-down circuitry. The highspeed shift register and data latches allow direct interfacing with microprocessor LSI-based systems. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. Both devices feature 60 V and -40 mA output ratings, allowing them to be used in many other peripheral power driver applications. These smart power drivers have been designed with BiMOS II logic for improved data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Use of these devices with TTL may require the use of appropriate pull-up resistors to ensure an input logic high. All devices can be operated over the ambient temperature range of 20°C to +85°C. The UCN5818AF is supplied in a 40-pin plastic dual in-line package with 0.600" (15.24 mm) row spacing. A copper lead frame, reduced supply current requirement, and low output saturation voltage permits operation with minimum junction temperature rise. The `A' package allows all 32 outputs to be operated at -25 mA continuously over the operating temperature range. For high-density packaging applications, the UCN5818EPF is furnished in a 44-lead plastic chip carrier (quad pack) for surface mounting on solder lands with 0.050" (1.27 mm) centers. The PLCC allows -25 mA continuous operation of all outputs simultaneously at ambient temperatures to 60°C. Similar devices are available as the UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5812AF/EPF (20 bits).
Data Sheet 26182.28D
V DD 44
43
V BB
42
41
40
6
3
5
4
2
1
OUT29
7 8 9 10
REGISTER REGISTER LATCHES
2
39 38 37 36
OUT 4
11 12 13 14 15 16 OUT19 17
35 34 33 19 32 31 30 OUT13
OUT 8
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ........... 15 V Driver Supply Voltage, VBB .......... 60 V Continuous Output Current, IOUT ....... -40 mA to +15 mA
Input Voltage Range, VIN ..... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD (UCN5818AF) .... 3.5 W* (UCN5818EPF) ....... 2.3 W Operating Temperature Range, TA ......... -20°C to +85°C Storage Temperature Range, TS ....... -55°C to +150°C
* Derate at rate of 28 mW/°C above TA = +25°C Derate at rate of 18 mW/°C above TA = +25°C
Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges.
en W em Ec N la R rep Od F de Tn O me Nm co e R
BLNK
29
NC
BLANKING 21
GROUND 22
OUT17
OUT15 26
NC
OUT18
STROBE
OUT14
OUT 6 1
CLOCK
NC
N 818 IG A6 S-- Et D
CLK
20
ST
27
LATCHES 28
18
23
19
24
25
Dwg. PP-059-2
FEATURES
s s s s s
60 V Source Outputs High-Speed Source Drivers To 3.3 MHz Data Input Rate Low-Output Saturation Voltages Active DMOS Pull-Downs
s Low-Power CMOS Logic and Latches s Reduced Supply Current Requirements s Improved Replacements for SN75518N/FN
Always order by complete part number, e.g., UCN5818EPF .
5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
UCN5818AF
LOAD SUPPLY SERIAL DATA OUT OUT 32 OUT 31 OUT 30 OUT 29 OUT 28 OUT 27 OUT 26 OUT 25 OUT 24 OUT 23 OUT 22 OUT 21 OUT 20 OUT 19 OUT 18 OUT 17 BLANKING GROUND 1 2 3 4 5 6 7 8 9 VBB VDD 40 39 38 37 36 35 34 33 32 LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 OUT 11 OUT 12 OUT 13 OUT 14 OUT 15 OUT 16 STROBE CLOCK
FUNCTIONAL BLOCK DIAGRAM
CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
BLANKING MOS BIPOLAR LOAD SUPPLY
REGISTER
REGISTER
LATCHES
LATCHES
VBB
10 11 12 13 14 15 16 17 18 19 20 BLNK
31 30 29 28 27 26 25 24 23 ST CLK 22 21
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
TYPICAL INPUT CIRCUIT
V DD
IN
Dwg. PP-029-4
3.0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
SUFFIX 'A', RJA = 36°C/W
Dwg. EP-010-5
2.0
TYPICAL OUTPUT DRIVER
V BB
1.5
SUFFIX 'EP', RJA = 54°C/W
1.0
OUT N
0.5
0 25 50 75 100 125 AMBIENT TEMPERATURE IN ° C 150
Dwg. No. A-14,219
Dwg. GP-025B
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1988, 2002 Allegro MicroSystems, Inc.
5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
ELECTRICAL CHARACTERISTICS at TA = + 25°C, VBB = 60 V unless otherwise noted.
L i m i t s @ VD D = 5 V Characteristic Output Leakage Current Output Voltage Symbol IC E X VOUT(1) VOUT(0) Test Conditions VOUT = 0 V, TA = +70°C IOUT = -25 mA IOUT = 1 mA IOUT = 2 mA Output Pull-Down Current IOUT(0) VOUT = 5 V to VBB VOUT = 20 V to VBB Input Voltage VIN(1) VIN(0) Input Current IIN(1) IIN(0) Serial Data Output Voltage VOUT(1) VOUT(0) Maximum Clock Frequency Supply Current f clk ID D ( 1 ) ID D ( 0 ) IB B ( 1 ) IBB(0) Blanking to Output Delay tP H L tP L H Output Fall Time Output Rise Time tf tr All Outputs High All Outputs Low Outputs High, No Load Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% CL = 30 pF, 90% to 10% CL = 30 pF, 10% to 90% VIN = VDD VIN = 0.8 V IOUT = -200 µA IOUT = 200 µA Mln. -- 58 -- -- 2.0 -- 3.5 -0.3 -- -- 4.5 -- 3.3* -- -- -- -- -- -- -- -- Typ. -5.0 58.5 2.0 -- 3.5 -- -- -- 0.05 -0.05 4.7 200 -- 100 100 3.0 10 2000 1000 1450 650 Max. -15 -- 3.0 -- -- -- 5.3 +0.8 0.5 -0.5 -- 250 -- 300 300 6.0 100 -- -- -- -- Limits @ VDD = 12 V Min. -- 58 -- -- -- 8.0 10.5 -0.3 -- -- 11.7 -- -- -- -- -- -- -- -- -- -- Typ. -5.0 58.5 -- 2.0 -- 13 -- -- 0.1 -0.1 11.8 100 -- 200 200 3.0 10 1000 850 650 700 Max. -15 -- -- 3.5 -- -- 12.3 +0.8 1.0 -1.0 -- 200 -- 500 500 6.0 100 -- -- -- -- Units µA V V V mA mA V V µA µA V mV MHz µA µA mA µA ns ns ns ns
Negative current is defined as coming out of (sourcing) the specified device terminal. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON, the information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.
CLOCK DATA IN
A
B
D
E C
F
STROBE BLANKING G OUTN
Dwg. No. A-12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns G. Typical Time Between Strobe Activation and Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.
TRUTH TABLE
Serial Shift Register Contents Data Clock I n p u t I n p u t I1 I2 I3 . . . IN-1 I N H L X H L R 1 R 2 ... R 1 R 2 ... R N-2 R N-1 R N-2 R N-1 R N-1 R N X X Serial Data Strobe Output Input R N-1 R N-1 RN X PN L H R 1 R 2 R 3 ... P1 P2 P3 ... X
L = Low Logic Level H = High Logic Level X = Irrelevant
Latch Contents I1 I2 I3 ... IN-1 I N Blanking
Output Contents I1 I2 I3 . . . I N - 1 I N
R 1 R 2 R 3 ... X X X ...
R N-1 R N PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L
P1 P2 P3 ...
PN-1 PN
X
X
...
P = Present State
R = Previous State
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
UCN5818AF
Dimensions in Inches (controlling dimensions)
40 21 0.015 0.008
0.700
MAX
0.580 0.485
0.600
BSC
1
2 0.070 0.030
3
4 2.095 1.980
20 0.100
BSC
0.005
MIN
0.250
MAX
0.015
MIN
0.200 0.115 0.022 0.014
Dwg. MA-003-40 in
Dimensions in Millimeters (for reference only)
21 0.381 0.204
40
17.78 14.73 12.32
MAX
15.24
BSC
1
2 1.77 0.77
3
4 53.2 50.3
2.54
BSC
20
0.13
MIN
6.35
MAX
0.39
MIN
5.08 2.93 0.558 0.356
Dwg. MA-003-40 mm
NOTES: 1. 2. 3. 4.
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 9 devices.
www.allegromicro.com
Others parts begin by 58
58-1 58-2
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