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Part: 6595
Category:
Power Management
Description:
Company: Allegro Micro Systems, Inc.
Datasheet: Download 6595 datasheet File size : 1680 kB
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Datasheet text preview:
6595
ADVANCE INFORMATION
(Subject to change without notice) January 24, 2000
POWER GROUND LOGIC SUPPLY SERIAL DATA IN OUT 0 OUT 1 OUT 2 OUT 3 REGISTER CLEAR OUTPUT ENABLE POWER GROUND POWER GROUND LOGIC GROUND SERIAL DATA OUT OUT 7 OUT 6 OUT 5 OUT 4 CLOCK STROBE POWER GROUND
8-BIT SERIAL-INPUT, DMOS POWER DRIVER
The A6595KA and A6595KLW combine an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serial-data input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. Similar devices with reduced rDS(on) are available as the A6A595. The A6595 DMOS open-drain outputs are capable of sinking up to 750 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. The A6595KA is furnished in a 20-pin dual in-line plastic package. The A6595KLW is furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85°C.
Data Sheet 26185.120
1 2 3 4 VDD
20 19 18 17
REGISTER
REGISTER
LATCHES
LATCHES
5 6 7 8 9 10 CLR OE
16 15 14 CLK ST 13 12 11
Dwg. PP-029-13
Note that the A6595KA (DIP) and the A6595KLW (SOIC) are electrically identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ....... 50 V Output Drain Current, Continuous, IO .. 250 mA* Peak, IOM ......... 750 mA* Peak, IOM ...... 2.0 A Single-Pulse Avalanche Energy, EAS ....... 75 mJ Logic Supply Voltage, VDD ......... 7.0 V Input Voltage Range, VI .. -0.3 V to +7.0 V Package Power Dissipation, PD .......... See Graph Operating Temperature Range, TA ......... -40°C to +125°C Storage Temperature Range, TS ......... -55°C to +150°C
* Each output, all outputs on. Pulse duration 100 µs, duty cycle 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges.
FEATURES
I 50 V Minimum Output Clamp Voltage I 250 mA Output Current (all outputs simultaneously) I 1.3 Typical rDS(on) I Low Power Consumption I Replacements for TPIC6595N and TPIC6595DW
Always order by complete part number: Part Number Package A6595KA 20-pin DIP A6595KLW 20-lead SOIC
RJA 55°C/W 70°C/W
RJC 25°C/W 17°C/W
6595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
9 12
LOGIC SYMBOL
G3 C2 R SRG8 C1 1D 2 4 5 6
A
2.0
SU FF IX
8 13
1.5
SU FF IX
'A ', R
J A=
3
'LW ', R
55 °C /W
1.0
J
=7 0° C/ W
7 14
0.5
15 16
0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150
2
17 18
Dwg. GS-004A
Dwg. FP-043
FUNCTIONAL BLOCK DIAGRAM
REGISTER CLEAR
(ACTIVE LOW)
CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE
(ACTIVE LOW)
V DD
LOGIC SUPPLY SERIAL DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
D-TYPE LATCHES
LOGIC GROUND
POWER GROUND
POWER GROUND
OUT 0
OUT N
Dwg. FP-013-5
Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, Allegro MicroSystems, Inc.
6595
8-BIT SERIAL-INPUT, DMOS POWER DRIVER
VDD IN
OUT
Dwg. EP-063-3
Dwg. EP-010-15
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
V DD
RECOMMENDED OPERATING CONDITIONS
over operating temperature range Logic Supply Voltage Range, VDD ...... 4.5 V to 5.5 V High-Level Input Voltage, VIH .... 0.85VDD Low-level input voltage, VIL ......... 0.15VDD
OUT
Dwg. EP-063-2
SERIAL DATA OUT TRUTH TABLE
Shift Register Contents Data Clock Input Input H L X I0 H L I1 I2 ... ... ... ... ... ... I6 I7 Serial Data Output Strobe R6 R6 R7 X P7 -- R0 R1 R2 P0 P1 P2 X L = Low Logic Level H = High Logic Level X = Irrelevant X X ... ... ... R6 R7 P6 P7 X X L H P0 P1 P2 H H H ... ... P6 P7 H H Latch Contents I0 I1 I2 ... I6 I7 Output Enable I0 Output Contents I1 I2 ... I6 I7
R0 R1 R0 R1
R5 R6 R5 R6 R6 R7 X X
R0 R1 R2 X X X
P0 P1 P2
P6 P7
P = Present State
R = Previous State
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6595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif 10 ns (unless otherwise specified).
Limits Characteristic Output Breakdown Voltage Off-State Output Current Static Drain-Source On-State Resistance Symbol V (BR)DSX I DSX Test Conditions IO = 1 mA VO = 40 V VO = 40 V, TA = 125°C Min. 50 -- -- -- -- -- -- -- -- -- IOH = -20 µA, VDD = 4.5 V IOH = -4 mA, VDD = 4.5 V V OL IOL = 20 µA, VDD = 4.5 V IOL = 4 mA, VDD = 4.5 V Prop. Delay Time tPLH tPHL Output Rise Time Output Fall Time Supply Current tr tf I DD(OFF) I DD(ON) IDD(fclk) IO = 250 mA, CL = 30 pF IO = 250 mA, CL = 30 pF IO = 250 mA, CL = 30 pF IO = 250 mA, CL = 30 pF All inputs low VDD = 5.5 V, Outputs on fclk = 5 MHz, CL = 30 pF, Outputs off 4.4 4.1 -- -- -- -- -- -- -- -- -- Typ. -- 0.05 0.15 1.3 2.0 1.3 250 -- -- 1.3 4.49 4.3 0.002 0.2 650 150 7500 425 15 150 0.6 Max. -- 1.0 5.0 2.0 3.2 2.0 -- 1.0 -1.0 -- -- -- 0.1 0.4 -- -- -- -- 100 300 5.0 Units V µA µA mA µA µA V V V V V ns ns ns ns µA µA mA
r DS(on)
IO = 250 mA, VDD = 4.5 V IO = 250 mA, VDD = 4.5 V, TA = 125°C IO = 500 mA, VDD = 4.5 V (see note)
Nominal Output Current Logic Input Current
I ON IIH IIL
VDS(on) = 0.5 V, TA = 85°C VI = VDD = 5.5 V VI = 0, VDD = 5.5 V
Logic Input Hysteresis SERIAL-DATA Output Voltage
V I(hys) V OH
Typical Data is at VDD = 5 V and is for design information only. NOTE -- Pulse test, duration 100 µs, duty cycle 2%.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6595
8-BIT SERIAL-INPUT, DMOS POWER DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C CLOCK A SERIAL DATA IN DATA tp SERIAL DATA OUT D STROBE
50% 50% 50%
B
50%
DATA E
OUTPUT ENABLE
LOW = ALL OUTPUTS ENABLED
tp OUT N
HIGH = OUTPUT OFF
50%
DATA
LOW = OUTPUT ON
Dwg. WP-029-2
HIGH = ALL OUTPUTS DISABLED OUTPUT ENABLE
50%
t PLH t PHL
90%
tf DATA
tr
OUT N
10%
Dwg. WP-030-2
A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ......... 10 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .... 10 ns C. Clock Pulse Width, tw(CLK) ............ 20 ns D. Time Between Clock Activation and Strobe, tsu(ST) ....... 50 ns E. Strobe Pulse Width, tw(ST) .... 50 ns F. Output Enable Pulse Width, tw(OE) ........ 4.5 µs NOTE Timing is representative of a 12.5 MHz clock. Higher speeds are attainable.
Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches.
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