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Part: 6810
Category:
Power Management
-> Voltage References
Description: Dabic-iv, 10-bit Serial-input, Latched Source Drivers
Company: Allegro Micro Systems, Inc.
Datasheet: Download 6810 datasheet File size : 74 kB
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Datasheet text preview:
Data Sheet 26182.124C
6810
The A6810xEP is LAST-TIME BUY -- Orders accepted until Oct. 31, 2003.
DABiC-IV, 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
The A6810 devices combine 10-bit CMOS shift registers, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuumfluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6810 feature an increased data input rate (compared with the older UCN/UCQ5810-F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, serial-data input rates of at least 10 MHz . A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are avail-able as the A6811 (12 bits), A6812 (20 bits), and A6818 (32 bits). The A6810 output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. The A6810 are available in two temperature ranges for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. They are provided in three package styles for through-hole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logicpower dissipation, and low output-saturation voltages allow all devices to source 25 mA from all outputs continuously over the maximum operating temperature range.
A6810xA
OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4
1 2 3 LATCHES 4 5 6 7 8 9 VDD ST CLK REGISTER REGISTER LATCHES
18 17 16 VBB 15 14 BLNK 13 12 11 10
OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT 1 OUT 2 OUT 3
Dwg. PP-029
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD .......... 7.0 V Driver Supply Voltage, VBB .......... 60 V Continuous Output Current Range, IOUT ....... -40 mA to +15 mA Input Voltage Range, VIN ..... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ....... See Graph Operating Temperature Range, TA (Suffix `E') ......... -40°C to +85°C (Suffix `S') ......... -20°C to +85°C Storage Temperature Range, TS ....... -55°C to +125°C
FEATURES
s Controlled Output Slew Rate s High-Speed Data Storage s 60 V Minimum Output Breakdown s Improved Replacements s High Data Input Rate for TL4810, UCN5810, s PNP Active Pull-Downs and UCQ5810 s Low Output-Saturation Voltages s Low-Power CMOS Logic and Latches Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6810SLW .
Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges.
6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
TYPICAL OUTPUT DRIVER
V BB
TYPICAL INPUT CIRCUIT
V DD
OUTN
IN
Dwg. EP-021-19
Dwg. EP-010-5
A6810xLW
The A6810xEP is LAST-TIME BUY -- Orders accepted until Oct. 31, 2003.
OUT 6
A6810xEP
OUT10 20 19 2 1
OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4 NO CONNECTION
1 2 3 LATCHES 4 5 6 7 8 9 10 NC VDD ST CLK REGISTER REGISTER LATCHES
20 19 18 VBB 17 16 BLNK 15 14 13 12 NC 11
OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT 1 OUT 2 OUT 3
3
CLOCK NC
4 5 6 7 8
CLK LATCHES REGISTER
18 V BB 17 16
SERIAL DATA OUT LOAD SUPPLY NC SERIAL DATA IN BLANKING
GROUND LOGIC SUPPLY
V DD ST
REGISTER 15 LATCHES BLNK 14
STROBE
12
10
11
OUT 5
OUT1
13
9
Dwg. PP-059
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
NO CONNECTION
2.5
SUFFIX 'EP', R JA = 59°C/W
Dwg. PP-029-2
2.0
SUFFIX 'A', R JA = 60°C/W
1.5
1.0
0.5
SUFFIX 'LW', R JA = 70°C/W
0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150
Dwg. GP-024-1
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1998, 2003 Allegro MicroSystems, Inc.
6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
FUNCTIONAL BLOCK DIAGRAM
CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
BLANKING MOS BIPOLAR LOAD SUPPLY
VBB
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
TRUTH TABLE
Serial Shift Register Contents Data Clock I n p u t I n p u t I1 I2 I3 . . . I N - 1 I N H L X H L R 1 R 2 ... R 1 R 2 ... R N-2 R N-1 R N-2 R N-1 R N-1 R N X X Serial Data Strobe Output Input R N-1 R N-1 RN X PN L H R 1 R 2 R 3 ... P1 P2 P3 ... X
L = Low Logic Level H = High Logic Level X = Irrelevant
Latch Contents I1 I2 I3 ... I N-1 I N B l a n k l n g
Output Contents I1 I2 I3 ... IN-1 IN
R 1 R 2 R 3 ... X X X ...
RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L
P1 P2 P3 ...
P N-1 P N
X
X
...
P = Present State
R = Previous State
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6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6810S-) or over operating temperature range (A6810E-), VBB = 60 V unless otherwise noted.
Limits @ VDD = 3.3 V Characteristic Output Leakage Current Output Voltage Symbol IC E X V OUT(1) V OUT(0) Output Pull-Down Current Input Voltage IO U T ( 0 ) VIN(1) VIN(0) Input Current IIN(1) IIN(0) Input Clamp Voltage Serial Data Output Voltage V IK V OUT(1) V OUT(0) Maximum Clock Frequency Logic Supply Current fc I DD(1) I DD(0) Load Supply Current IBB(1) IB B ( 0 ) Blanking-to-Output Delay td i s ( B Q ) t en(BQ) Strobe-to-Output Delay tp ( S T H - Q L ) t p(STH-QH) Output Fall Time Output Rise Time Output Slew Rate tf tr dV/dt All Outputs High All Outputs Low All Outputs High, No Load All Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF IOUT = ±200 µA VIN = VDD VIN = 0 V IIN = -200 µA IOUT = -200 µA IOUT = 200 µA Test Conditions VOUT = 0 V IOUT = -25 mA IOUT = 1 mA VOUT = 5 V to VBB Mln. -- 57.5 -- 2.5 2.2 -- -- -- -- 2.8 -- 10* -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 <-0.01 -0.8 3.05 0.15 -- 0.25 0.25 1.5 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 Max. -15 -- 1.5 -- -- 1.1 1.0 -1.0 -1.5 -- 0.3 -- 0.75 0.75 3.0 20 2.0 3.0 2.0 3.0 12 12 20 -- Limits @ VDD = 5 V Min. -- 57.5 -- 2.5 3.3 -- -- -- -- 4.5 -- 10* -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 <-0.01 -0.8 4.75 0.15 -- 0.3 0.3 1.5 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 Max. -15 -- 1.5 -- -- 1.7 1.0 -1.0 -1.5 -- 0.3 -- 1.0 1.0 3.0 20 2.0 3.0 2.0 3.0 12 12 20 -- Units µA V V mA V V µA µA V V V MHz mA mA mA µA µs µs µs µs µs µs V/µs ns
Clock-to-Serial Data Out Delay tp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at TA = +25°C. *Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C CLOCK A SERIAL DATA IN DATA
50%
B
50%
t p(CH-SQX) SERIAL DATA OUT D STROBE
50% 50%
DATA E
BLANKING
LOW = ALL OUTPUTS ENABLED t p(STH-QH) t p(STH-QL)
90%
OUT N
DATA
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED) BLANKING
50%
t dis(BQ) t en(BQ) OUT N tr
90% 10%
tf
DATA
Dwg. WP-030
A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ........ 25 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ..... 25 ns C. Clock Pulse Width, tw(CH) ..... 50 ns D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns E. Strobe Pulse Width, tw(STH) ............ 50 ns NOTE Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency.
SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.
Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The
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