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Part: 6812
Category:
Power Management
-> Voltage References
Description: Dabic-iv, 20-bit Serial-input, Latched Source Driver
Company: Allegro Micro Systems, Inc.
Datasheet: Download 6812 datasheet File size : 74 kB
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Datasheet text preview:
Data Sheet 26182.126B
6812
A6812xA (DIP)
LOAD SUPPLY SERIAL DATA OUT OUT 20 OUT 19 OUT 18 OUT 17 OUT 16 OUT 15 OUT 14 OUT 13 OUT 12 OUT 11 BLANKING GROUND 1 2 3 4 5 6 VBB VDD 28 27 26 25 24 23 LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 STROBE CLOCK
DABiC-IV, 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
The A6812 devices combine a 20-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6812 features an increased data input rate (compared with the older UCN/UCQ5812-F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, they will operate to at least 10 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6809 and A6810 (10 bits), A6811 (12 bits), and A6818 (32 bits). The A6812 output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Three temperature ranges are available for optimum performance in commercial (suffix S-), industrial (suffix E-), or automotive (suffix K-) applications. Package styles are provided for through-hole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logicpower dissipation, and low output-saturation voltages allow these drivers to source 25 mA from all outputs continuously to more than +43°C (suffix -LW), +61°C (suffix -EP), or +77°C (suffix -A).
REGISTER
REGISTER
LATCHES
LATCHES
7 8 9 10 11 12 13 14 BLNK
22 21 20 19 18 17 ST CLK 28 16 27 15
Dwg. PP-029-7
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD .......... 7.0 V Driver Supply Voltage, VBB .......... 60 V Continuous Output Current Range, IOUT ....... -40 mA to +15 mA Input Voltage Range, VIN ..... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ....... See Graph Operating Temperature Range, TA (Suffix `E') ......... -40°C to +85°C (Suffix `K') ....... -40°C to +125°C (Suffix `S') ......... -20°C to +85°C Storage Temperature Range, TS ....... -55°C to +125°C
Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges.
FEATURES
s Controlled Output Slew Rate s Low Output-Saturation Voltages s High-Speed Data Storage s Low-Power CMOS Logic s 60 V Minimum and Latches Output Breakdown s Improved Replacements s High Data Input Rate for TL5812, UCN5812, s PNP Active Pull-Downs and UCQ5812 Complete part number includes a suffix to identify operating temperature range (E-, K-, or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6812SLW .
6812
20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
A6812xEP (PLCC)
SERIAL DATA OUT LOGIC SUPPLY LOAD SUPPLY SERIAL DATA IN OUT20 OUT19
LOAD SUPPLY SERIAL DATA OUT OUT 20 1 2 3 4 5 6 REGISTER REGISTER LATCHES LATCHES 7 8 9 10 11 12 13 14 BLNK ST CLK
A6812xLW (SOIC)
VBB VDD 28 27 26 25 24 23 22 21 20 19 18 17 28 16 27 15 LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 STROBE CLOCK
V DD 28
V BB
27
26
4
3
2
1
OUT 1
OUT18
5 6
25 24
OUT 2
OUT 19 OUT 18 OUT 17 OUT 16 OUT 15 OUT 14
REGISTER
REGISTER
LATCHES
LATCHES
7 8 9 10 OUT12 11
23 22 21 20 19 OUT 8
OUT 13 OUT 12
CLK 12 14
ST 17
13
15
16
18
OUT11
GROUND
BLANKING
STROBE
CLOCK
OUT 0 1
OUT9
OUT 11 BLANKING
Dwg. PP-059-1
GROUND
TYPICAL INPUT CIRCUIT
Dwg. PP-029-8
VDD
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
SU FF IX
IX FF SU
IN
2.0
'E P' ,R
', R 'A
A=
J
1.5
SU FF IX
55 °C /W
J A
= /W °C 45
'LW ', R
Dwg. EP-010-5
J
A
TYPICAL OUTPUT DRIVER
V BB
1.0
=
66 °C /W
0.5
OUTN
0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150
Dwg. EP-021-19
Dwg. GP-024-2
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, 2002 Allegro MicroSystems, Inc.
6812
20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
FUNCTIONAL BLOCK DIAGRAM
CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
BLANKING MOS BIPOLAR LOAD SUPPLY
VBB
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
TRUTH TABLE
Serial Shift Register Contents Data Clock I n p u t I n p u t I1 I2 I3 . . . IN-1 I N H L X H L R 1 R 2 ... R 1 R 2 ... R N-2 R N-1 R N-2 R N-1 R N-1 R N X X Serial Data Strobe Output Input R N-1 R N-1 RN X PN L H R 1 R 2 R 3 ... P1 P2 P3 ... X
L = Low Logic Level H = High Logic Level X = Irrelevant
Latch Contents I1 I2 I3 ... IN-1 I N Blanklng
Output Contents I1 I2 I3 . . . I N - 1 I N
R 1 R 2 R 3 ... X X X ...
R N-1 R N PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L
P1 P2 P3 ...
PN-1 PN
X
X
...
P = Present State
R = Previous State
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6812
20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating temperature range (A6812E- or A6812K-), VBB = 60 V unless otherwise noted.
Limits @ VDD = 3.3 V Characteristic Output Leakage Current Output Voltage Symbol IC E X V OUT(1) V OUT(0) Output Pull-Down Current Input Voltage IO U T ( 0 ) VIN(1) VIN(0) Input Current IIN(1) IIN(0) Input Clamp Voltage Serial Data Output Voltage V IK V OUT(1) V OUT(0) Maximum Clock Frequency Logic Supply Current fc I DD(1) I DD(0) Load Supply Current IB B ( 1 ) IB B ( 0 ) Blanking-to-Output Delay tdis(BQ) t en(BQ) Strobe-to-Output Delay tp ( S T H - Q L ) t p(STH-QH) Output Fall Time Output Rise Time Output Slew Rate tf tr dV/dt All Outputs High All Outputs Low All Outputs High, No Load All Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF IOUT = ±200 µA VIN = VDD VIN = 0 V IIN = -200 µA IOUT = -200 µA IOUT = 200 µA Test Conditions VOUT = 0 V IOUT = -25 mA IOUT = 1 mA VOUT = 5 V to VBB Mln. -- 57.5 -- 2.5 2.2 -- -- -- -- 2.8 -- 10* -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 <-0.01 -0.8 3.05 0.15 -- 0.25 0.25 3.0 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 Max. -15 -- 1.5 -- -- 1.1 1.0 -1.0 -1.5 -- 0.3 -- 0.75 0.75 6.0 20 2.0 3.0 2.0 3.0 12 12 20 -- Limits @ VDD = 5 V Min. -- 57.5 -- 2.5 3.3 -- -- -- -- 4.5 -- 10* -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 <-0.01 -0.8 4.75 0.15 -- 0.3 0.3 3.0 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 Max. -15 -- 1.5 -- -- 1.7 1.0 -1.0 -1.5 -- 0.3 -- 1.0 1.0 6.0 20 2.0 3.0 2.0 3.0 12 12 20 -- Units µA V V mA V V µA µA V V V MHz mA mA mA µA µs µs µs µs µs µs V/µ s ns
Clock-to-Serial Data Out Delay tp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at TA = +25°C. * Operation at a clock frequency greater than the specified minimum is possible but not warranteed.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6812
20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C CLOCK A SERIAL DATA IN DATA
50%
B
50%
t p(CH-SQX) SERIAL DATA OUT D STROBE
50% 50%
DATA E
BLANKING
LOW = ALL OUTPUTS ENABLED t p(STH-QH) t p(STH-QL)
90%
OUT N
DATA
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED) BLANKING
50%
t dis(BQ) t en(BQ) OUT N tr
90% 10%
tf
DATA
Dwg. WP-030
A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ..... 25 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ........... 25 ns C. Clock Pulse Width, tw(CH) ........... 50 ns D. Time Between Clock Activation and Strobe, tsu(C) .... 100 ns E. Strobe Pulse Width, tw(STH) ......... 50 ns NOTE Timing is representative of a 10 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.
data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.
Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift
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