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Part: 6B259
Category:
Power Management
Description:
Company: Allegro Micro Systems, Inc.
Datasheet: Download 6B259 datasheet File size : 286 kB
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6B259
ADVANCE INFORMATION
(Subject to change without notice) January 24, 2000
8-BIT ADDRESSABLE DMOS POWER DRIVER
The A6B259KA and A6B259KLW combine a 3-to-8 line CMOS decoder and accompanying data latches, control circuitry, and DMOS outputs in a multi-functional power driver capable of storing single-line data in the addressable latches or use as a decoder or demuliplexer. Driver applications include relays, solenoids, and other mediumcurrent or high-voltage peripheral power loads. The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pullup resistors to ensure an input logic high. Four modes of operation are selectable with the CLEAR and ENABLE inputs. The A6B259KA/KLW DMOS open-drain outputs are capable of sinking up to 500 mA. Similar devices with reduced rDS(on) are available as the A6259KA/KLW. The A6B259KA is furnished in a 20-pin dual in-line plastic package. The A6B259KLW is furnished in a 20-lead wide-body, small-outline plastic package (SOIC) with gull-wing leads for surfacemount applications. Copper lead frames, reduced supply current requirements, and low on-state resistance allow either device to sink 150 mA from all outputs continuously, to ambient temperatures greater than 85°C.
Data Sheet 26186.122
NO (INTERNAL) CONNECTION LOGIC SUPPLY S 0 (LSB) OUT 0 OUT 1 OUT 2 OUT 3 S1 LOGIC GROUND POWER GROUND
1 2 3 4
NC VDD
NC
20 19 18 17
NO (INTERNAL) CONNECTION CLEAR DATA OUT 7 OUT 6 OUT 5 OUT 4 ENABLE S 2 (MSB) POWER GROUND
DECODER LOGIC
LATCHES
LATCHES
5 6 7 8 9 10
16 15 14 EN 13 12 11
Dwg. PP-050-1
Note that the A6B259KA (DIP) and the A6B259KLW (SOIC) are electrically identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ....... 50 V Output Drain Current, Continuous, IO .. 150 mA* Peak, IOM .. 500 mA Single-Pulse Avalanche Energy, EAS ....... 30 mJ Logic Supply Voltage, VDD ......... 7.0 V Input Voltage Range, VI .. -0.3 V to +7.0 V Package Power Dissipation, PD .......... See Graph Operating Temperature Range, TA ......... -40°C to +125°C Storage Temperature Range, TS ......... -55°C to +150°C
* Each output, all outputs on. Pulse duration 100 µs, duty cycle 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges.
FEATURES
s 50 V Minimum Output Clamp Voltage s 150 mA Output Current (all outputs simultaneously) s 5 Typical rDS(on) s Low Power Consumption s Replacements for TPIC6B259N and TPIC6B259DW
Always order by complete part number: Part Number Package A6B259KA 20-pin DIP A6B259KLW 20-lead SOIC
RJA 55°C/W 70°C/W
RJC 25°C/W 17°C/W
6B259
8-BIT ADDRESSABLE DMOS POWER DRIVER
LOGIC SYMBOL
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
3 8 12 13 18 0 8M 0/7 2 G8 Z9 Z10 9,0D 10,0R 9,1D 10,1R 9,2D 10,2R 9,3D 10,3R 9,4D 10,4R 9,5D 10,5R 9,6D 10,6R 4 5 6 7 14 15 16 17
2.0
SU FF IX
1.5
SU FF IX
'A ', R
19
A=
J
'LW ', R
55 °C /W
1.0
J
A
=7 0° C/ W
0.5
0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150
9,7D 10,7R
Dwg. GS-004A
Dwg. FP-046
V IN
DD
OUT
Dwg. EP-063
Dwg. EP-010-15
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
FUNCTION TABLE
Inputs CLEAR ENABLE DATA
H H H L L L L L H L L H H L X H L X
LATCH SELECTION TABLE
Function
Addressable Latch Memory 8-Line Demultiplexer Clear R = Previous State
Addressed OUTPUT
L H R L H H
Other OUTPUTs
R R R H H H
Select Inputs Addressed S2 (MSB) S1 S0 (LSB) OUTPUT
L L L L H H H L L H H L L H L H L H L H L 0 1 2 3 4 5 6
L = Low Logic Level
H = High Logic Level
X = Irrelevant
H
H
H
7
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, Allegro MicroSystems, Inc.
6B259
8-BIT ADDRESSABLE DMOS POWER DRIVER
FUNCTIONAL BLOCK DIAGRAM
S0 (LSB) D C1 CLR D C1 CLR S1 D C1 CLR D C1 CLR S2 (MSB) D C1 CLR D V DD C1 CLR D C1 CLR DATA ENABLE
(ACTIVE LOW)
OUT 0
OUT 1
OUT 2
OUT 3
OUT 4
LOGIC SUPPLY
OUT 5
OUT 6
D C1 CLR
OUT 7 GROUND
CLEAR
(ACTIVE LOW)
Dwg. FP-047
Grounds (terminals 9, 10, and 11) must be connected externally to a single point.
www.allegromicro.com
6B259
8-BIT ADDRESSABLE DMOS POWER DRIVER
RECOMMENDED OPERATING CONDITIONS
over operating temperature range Logic Supply Voltage Range, VDD ...... 4.5 V to 5.5 V High-Level Input Voltage, VIH .... 0.85VDD Low-level input voltage, VIL ......... 0.15VDD
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif 10 ns (unless otherwise specified).
Limits Characteristic Logic Supply Voltage Output Breakdown Voltage Off-State Output Current Static Drain-Source On-State Resistance Symbol VDD V (BR)DSX I DSX Test Conditions Operating IO = 1 mA VO = 40 V, VDD = 5.5 V VO = 40 V, VDD = 5.5 V, TA = 125°C Min. 4.5 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. 5.0 -- 0.1 0.15 4.2 6.8 5.5 90 -- -- 150 90 200 200 20 150 Max. 5.5 -- 5.0 8.0 5.7 9.5 8.0 -- 1.0 -1.0 -- -- -- -- 100 300 Units V V µA µA mA µA µA ns ns ns ns µA µA
r DS(on)
IO = 100 mA, VDD = 4.5 V IO = 100 mA, VDD = 4.5 V, TA = 125°C IO = 350 mA, VDD = 4.5 V (see note)
Nominal Output Current Logic Input Current
I ON I IH I IL
VDS(on) = 0.5 V, TA = 85°C VI = VDD = 5.5 V VI = 0, VDD = 5.5 V IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF VDD = 5.5 V, Outputs off VDD = 5.5 V, Outputs on
Prop. Delay Time
t PLH t PHL
Output Rise Time Output Fall Time Supply Current
tr tf I DD(OFF) I DD(ON)
Typical Data is at VDD = 5 V and is for design information only. NOTE -- Pulse test, duration 100 µs, duty cycle 2%.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6B259
8-BIT ADDRESSABLE DMOS POWER DRIVER
FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS
ENABLE
Four modes of operation are selectable by controlling the CLEAR and ENABLE inputs as shown above.
50%
DATA
t PLH ADDRESSED OUTPUT
t PHL
90%
10%
In the addressable-latch mode, data at the DATA input is written into the addressed transparent latch. The addressed output inverts the data input with all other outputs remaining in their previous states.
Dwg. WP-036
tr
tf
OUTPUT SWITCHING TIME
In the memory mode, all outputs remain in their previous states and are unaffected by the DATA or address (Sn) inputs. To prevent entering erroneus data in the latches, ENABLE should be held HIGH while the address lines are changing. In the demultiplexing/decoding mode, the addressed output inverts the data input and all other outputs are OFF. In the clear mode, all outputs are OFF and are unaffected by the DATA or address (SN) inputs.
ENABLE t su(D) DATA
50%
50%
t h(D)
t w(D)
Dwg. WP-037
DATA INPUT REQUIREMENTS
Data Active Time Before Enable (Data Set-Up Time), tsu(D) .... 20 ns Data Active Time After Enable (Data Hold Time), th(D) ......... 20 ns Data Pulse Width, tw(D) ....... 40 ns Input Logic High, VIH ...... 0.85VCC Input Logic Low, VIL ....... 0.15VCC
Given the appropriate inputs, when DATA is LOW for a given address, the output is OFF; when DATA is HIGH, the output is ON and can sink current.
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Others parts begin by 6b
6B-1
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