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Part: 6B273
Category:
Interface and Interconnect
-> Drivers
-> Latched/Addressable
Description: 8-bit Latched Dmos Power Driver
Company: Allegro Micro Systems, Inc.
Datasheet: Download 6B273 datasheet File size : 286 kB
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Datasheet text preview:
6B273
CLEAR IN 1 IN 2 OUT 1 OUT 2 OUT 3 OUT 4 IN 3 IN 4 GROUND 1 2 3 4 VDD 20 19 18 17 LOGIC SUPPLY IN 8 IN 7 OUT 8 OUT 7 OUT 6 OUT 5 IN 6 IN 5 STROBE
8-BIT LATCHED DMOS POWER DRIVER
The A6B273KA and A6B273KLW combine eight (positive-edgetriggered D-type) data latches and DMOS outputs for systems requiring relatively high load power. Driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. The DMOS output inverts the DATA input. All of the output drivers are disabled (the DMOS sink drivers turned OFF) with the CLEAR input low. The A6B273KA/KLW DMOS open-drain outputs are capable of sinking up to 500 mA. Similar devices with reduced rDS(on) are available as the A6273KA/KLW. The A6B273KA is furnished in a 20-pin dual in-line plastic package. The A6B273KLW is furnished in a 20-lead wide-body, small-outline plastic package (SOIC) with gull-wing leads for surfacemount applications. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 8 5° C .
Data Sheet 26180.122
LATCHES
LATCHES
5 6 7 8 9 10
16 15 14 13 12 11
Dwg. PP-015-2A
Note that the A6B273KA (DIP) and the A6B273KLW (SOIC) are electrically identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ....... 50 V Output Drain Current, Continuous, IO .. 150 mA* Peak, IOM .. 500 mA Single-Pulse Avalanche Energy, EAS ....... 30 mJ Logic Supply Voltage, VDD ......... 7.0 V Input Voltage Range, VI .. -0.3 V to +7.0 V Package Power Dissipation, PD .......... See Graph Operating Temperature Range, TA ......... -40°C to +125°C Storage Temperature Range, TS ......... -55°C to +150°C
* Each output, all outputs on. Pulse duration 100 µs, duty cycle 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges.
FEATURES
s 50 V Minimum Output Clamp Voltage s 150 mA Output Current (all outputs simultaneously) s 5 Typical rDS(on) s Low Power Consumption s Replacements for TPIC6B273N and TPIC6B273DW
Always order by complete part number: Part Number Package A6B273KA 20-pin DIP A6B273KLW 20-lead SOIC
RJA 55°C/W 70°C/W
RJC 25°C/W 17°C/W
6B273 8-BIT LATCHED DMOS POWER DRIVER
LOGIC SYMBOL
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
1 11 R C1 1D 1D 1D 1D 1D 1D 1D 1D 4 5 6 7 14 15 16 17
2.0
SU FF IX
2
'A ', R
1.5
J
3
A=
1.0
SU FF IX 'LW ', R
55 °C /W
8 9
JA = 90
°C /W
12 13 18
0.5
0 25 50 75 100 125 AMBIENT TEMPERATURE IN ° C 150
19
Dwg. GS-004B
Dwg. FP-046-1A
VDD IN
OUT
Dwg. EP-010-16
Dwg. EP-063
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
FUNCTION TABLE
CLEAR
L H H H
Inputs STROBE
X
INX
X H L X
OUTX
H L H R
L
L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2002 Allegro MicroSystems, Inc.
6B273 8-BIT LATCHED DMOS POWER DRIVER
FUNCTIONAL BLOCK DIAGRAM
IN 1 STROBE
D C1 CLR
OUT 1
IN2 LOGIC SUPPLY IN 3 V DD
D C1 CLR D C1 CLR
OUT 2
OUT 3
IN 4
D C1 CLR
OUT 4
IN5
D C1 CLR
OUT 5
IN6
D C1 CLR
OUT 6
IN 7
D C1 CLR
OUT 7
IN8
D C1
OUT 8 GROUND
CLEAR
(ACTIVE LOW)
CLR
Dwg. FP-016-2
www.allegromicro.com
6B273 8-BIT LATCHED DMOS POWER DRIVER
RECOMMENDED OPERATING CONDITIONS
over operating temperature range Logic Supply Voltage Range, VDD ...... 4.5 V to 5.5 V High-Level Input Voltage, VIH .... 0.85VDD Low-level input voltage, VIL ......... 0.15VDD
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif 10 ns (unless otherwise specified).
Limits Characteristic Logic Supply Voltage Output Breakdown Voltage Off-State Output Current Static Drain-Source On-State Resistance Symbol VDD V (BR)DSX I DSX Test Conditions Operating IO = 1 mA VO = 40 V, VDD = 5.5 V VO = 40 V, VDD = 5.5 V, TA = 125°C Min. 4.5 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. 5.0 -- 0.1 0.15 4.2 6.8 5.5 90 -- -- 150 90 200 200 20 150 Max. 5.5 -- 5.0 8.0 5.7 9.5 8.0 -- 1.0 -1.0 -- -- -- -- 100 300 Units V V µA µA mA µA µA ns ns ns ns µA µA
r DS(on)
IO = 100 mA, VDD = 4.5 V IO = 100 mA, VDD = 4.5 V, TA = 125°C IO = 350 mA, VDD = 4.5 V (see note)
Nominal Output Current Logic Input Current
I ON I IH I IL
VDS(on) = 0.5 V, TA = 85°C VI = VDD = 5.5 V VI = 0, VDD = 5.5 V IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF VDD = 5.5 V, Outputs off VDD = 5.5 V, Outputs on
Prop. Delay Time
t PLH t PHL
Output Rise Time Output Fall Time Supply Current
tr tf I DD(OFF) I DD(ON)
Typical Data is at VDD = 5 V and is for design information only. NOTE -- Pulse test, duration 100 µs, duty cycle 2%.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6B273 8-BIT LATCHED DMOS POWER DRIVER
TIMING REQUIREMENTS
INx
50%
50%
t su(D) STROBE
t h(D)
50%
t su(D)
t h(D)
t PLH OUTPUTx
10%
t PHL
90%
tr
tf
Dwg. WP-036-1
Input Active Time Before Strobe (Data Set-Up Time), tsu(D) .... 20 ns Input Active Time After Strobe (Data Hold Time), th(D) ......... 20 ns Input Pulse Width, tw(D) ....... 40 ns Input Logic High, VIH ...... 0.85VCC Input Logic Low, VIL ....... 0.15VCC
TEST CIRCUITS
INPUT +15 V
10.5 200 mH
tav IAS = 500 mA IO DUT
Single-Pulse Avalanche Energy Test Circuit and Waveforms
OUT
VO
V(BR)DSX
VO(ON)
Dwg. EP-066
E A S = IA S x V ( B R ) D S X x tA V / 2
www.allegromicro.com
Others parts begin by 6b
6B-1
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