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Details, datasheet, quote on part number:8902A
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| Part: | 8902A |
| Category: | Power Management => Motor Controller/Drivers |
| Description: | 3-phase Brushless DC Motor Controller/driver With Back-emf Sensing |
| Company: | Allegro Micro Systems, Inc. |
| Datasheet: | Download 8902A datasheet File size : 160 kB |
| Request For quote: | Find where to buy 8902A
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Datasheet text preview:
8902A
3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING
LOAD SUPPLY C D2 C WD CST OUTA GROUND GROUND OUT B OUT C CENTERTAP BRAKE C RES 1 2 V BB COMMUTATION DELAY 24 23 C D1 DATA IN CLOCK CHIP SELECT RESET GROUND GROUND DATA OUT OSCILLATOR LOGIC SUPPLY SECTOR DATA FILTER
Data Sheet 26301.2
SERIAL PORT
3 4 5 6 7 8 9 9 10 11 12 BOOST CHARGE PUMP
22 21 20 19 18
The A8902CLBA is a three-phase brushless dc motor controller/ driver for use in 5 V or 12 V hard-disk drives. The three half-bridge outputs are low on-resistance n-channel DMOS devices capable of driving up to 1.25 A. The A8902CLBA provides complete, reliable, self-contained back-EMF sensing motor startup and running algorithms. A programmable digital frequency-locked loop speed control circuit together with the linear current control circuitry provides precise motor speed regulation. A serial port allows the user to program various features and modes of operation, such as the speed control parameters, startup current limit, sleep mode, diagnostic modes, and others. The A8902CLBA is fabricated in Allegro's BCD (Bipolar CMOS DMOS) process, an advanced mixed-signal technology that combines bipolar, analog and digital CMOS, and DMOS power devices. The A8902CLBA is provided in a 24-lead wide-body SOIC batwing package. It provides for the smallest possible construction in surface-mount applications.
MUX FLL VDD
17 16 15 14 13
Dwg. PP-040B
FEATURES
s s s s s s s s s s s s s s s s s DMOS Outputs Low rDS(on) Startup Commutation Circuitry Back-EMF Commutation Circuitry Serial Port Interface Frequency-Locked Loop Speed Control Sector Data Tachometer Signal Input Programmable Start-Up Current Diagnostics Mode Sleep Mode Linear Current Control Internal Current Sensing Dynamic Braking Through Serial Port Power-Down Dynamic Braking System Diagnostics Data Out Data Out Ported in Real Time Internal Thermal Shutdown Circuitry
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB . . . . . . . . . . 14 V Output Current, IOUT . . . . . . . . . . . . ±1.25 A Logic Supply Voltage, VDD . . . . . . . . . 6.0 V Logic Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Package Power Dissipation, PD See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . 0°C to +70°C Junction Temperature, TJ . . . . . . . +150°C Storage Temperature Range, TS . . . . . . . . . . . . . . . -55°C to +150°C
Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. Output current rating may be restricted to a value determined by system concerns and factors. These include: system duty cycle and timing, ambient temperature, and use of any heatsinking and/or forced cooling. For reliable operation, the specified maximum junction temperature should not be exceeded.
Always order by complete part number, e.g., A8902CLBA .
8902A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
FUNCTIONAL BLOCK DIAGRAM
LOGIC SUPPLY
15
C D1
24
C D2
2
C ST
4
BRAKE
11
C RES
12
VDD BOOST CHARGE PUMP
1
BRAKE
VBB
LOAD SUPPLY OUT A OUT B OUTC
COMMUTATION LOGIC
OUT A OUT B OUT C CENTERTAP C WD
10
START-UP OSC. BLANK
SEQUENCE LOGIC
FCOM COMMUTATION DELAY
5
8
9
3
WATCHDOG TIMER
SECTOR 14 DATA OSC 16 FREQUENCYLOCKED LOOP CHARGE PUMP CURRENT CONTROL RS
6-7
GROUND
DATA IN
23
SERIAL PORT
MUX
TSD
18-19
GROUND
21
22
20
17
13
CHIP SELECT
CLOCK
RESET
DATA OUT
FILTER
Dwg. FP-034
ALLOWABLE PACKAGE POWER DISSIPATION in WATTS
2.5
RJT = 6°C/W
2.0
1.5
1.0
R JA = 55°C/W
0.5
0 25 50 75 100 125 150
Dwg. GP-019B
TEMPERATURE in °C
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1992, 1995 Allegro MicroSystems, Inc.
8902A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V
Limits Characteristic Logic Supply Voltage Logic Supply Current Symbol VDD I DD Operating Operating Sleep Mode Load Supply Voltage Thermal Shutdown Thermal Shutdown Hysteresis Output Drivers Output Leakage Current IDSX VBB = 14 V, VOUT = 14 V VBB = 14 V, VOUT = 0 V Total Output ON Resistance (Source + Sink + RS) Output Sustaining Voltage Clamp Diode Forward Voltage Control Logic Logic Input Voltage VIN(0) VIN(1) Logic Input Current I IN(0) I IN(1) DATA Output Voltage VOUT(0) VOUT(1) CST Current I CST SECTOR DATA, RESET, CLK, CHIP SELECT, OSC VIN = 0 V VIN = 5.0 V IOUT = 500 µA IOUT = -500 µA Charging Discharging CST Threshold VCSTH VCSTL Filter Current IFILTER Charging Discharging Leakage, VFILTER = 2.5 V Filter Threshold CD Current (CD1 or CD2) CD Current Matching CD Threshold -- VCDTH VFILTERTH I CD Charging Discharging ICD(DISCHRG)/ICD(CHRG) -0.3 3.5 -- -- -- 3.5 -9.0 -- 2.25 0.85 -9.0 9.0 -- 1.57 -18 32 1.8 2.25 -- -- -- -- -- -- -10 500 2.5 1.0 -10 10 -- 1.85 -20 40 2.0 2.5 1.5 5.3 -0.5 1.0 1.5 -- -11 -- 2.75 1.15 -11 11 5.0 2.13 -22 48 2.2 2.75 V V µA µA V V µA µA V V µA µA nA V µA µA -- V r DS(on) IOUT = 600 mA -- -- -- 1.0 -1.0 1.0 300 -300 1.4 µA µA VBB TJ T J Operating Test Conditions Min. 4.5 -- -- 4.0 -- -- Typ. 5.0 7.5 250 -- 165 20 Max. 5.5 10 500 14 -- -- Units V mA µA V °C °C
VDS(sus) VF
VBB = 14 V, IOUT = IOUT(MAX), L = 3 mH IF = 1.0 A
14 --
-- 1.25
-- 1.5
V V
Continued next page ...
8902A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS continued
Limits Characteristic CWD Current CWD Threshold Voltage Symbol I CWD VTL VTH Max. FLL Oscillator Frequency I OUT ( M A X ) fOSC -- VDD = 5.0 V, TA = 25°C D3 = 0, D4 = 0 D3 = 0, D4 = 1 D3 = 1, D4 = 0 D3 = 1, D4 = 1 BRAKE Threshold BRAKE Hysteresis Current Transconductance Gain Centertap Resistors Back-EMF Hysteresis VBRK IBRKL gm RCT -- VBEMF - VCTAP at FCOM Transition VBRK = 750 mV Charging Test Conditions Min. -9.0 0.22 2.25 12 1.0 0.9 0.5 -- 1.5 -- 0.42 5.0 5.0 -5.0 Typ. -10 0.25 2.5 -- 1.2 1.0 0.6 250 1.75 20 0.50 10 20 -20 Max. -11 0.28 2.75 -- 1.4 1.1 0.7 -- 2.0 -- 0.58 13 37 -37 Units µA V V MHz A A A mA V µA A/V k mV mV
SERIAL PORT TIMING CONDITIONS
CHIP SELECT E CLOCK C DATA D C D A B
Dwg. WP-019
A. Minimum CHIP SELECT setup time before CLOCK rising edge .......... 100 ns B. Minimum CHIP SELECT hold time after CLOCK rising edge ...... 150 ns C. Minimum DATA setup time before CLOCK rising edge ...... 150 ns D. Minimum DATA hold time after CLOCK rising edge ..... 150 ns E. Minimum CLOCK low time before CHIP SELECT .......... 50 ns F. Maximum CLOCK frequency ..... 3.3 MHz
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
8902A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
TERMINAL FUNCTIONS
Term. 1 2 3 4 5 6-7 8 9 10 11 Terminal Name LOAD SUPPLY CD2 CWD CST OUT A GROUND OUT B OUTC CENTERTAP BRAKE Function VBB; the 5 V or 12 V motor supply. One of two capacitors used to generate the ideal commutation points from the back-EMF zero crossing points. Timing capacitor used by the watchdog circuit to disable the back-EMF comparators during commutation transients, and to detect incorrect motor position. Startup oscillator timing capacitor. Power amplifier A output to motor. Power and logic ground and thermal heat sink. Power amplifier B output to motor. Power amplifier C output to motor. Motor centertap connection for back-EMF detection circuitry. Active low turns ON all three sink drivers shorting the motor windings to ground. External capacitor and resistor at BRAKE provide brake delay. The brake function can also be controlled via the serial port. External reservoir capacitor used to hold charge to drive the source drivers' gates. Also provides power for brake circuit. Analog voltage input to control motor current. Also, compensation node for internal speed control loop. External tachometer input. Can use sector or index pulses from disk to provide precise motor speed feedback to internal frequency-locked loop. VDD; the 5 V logic supply. Clock input for the speed reference counter. Typical max. frequency is 10 MHz. Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real time, controlled by 2-bit multiplexer in serial port. Power and logic ground and thermal heat sink. When pulled low forces the chip into sleep mode; clears all serial port bits. Strobe input (active low) for data word. Clock input for serial port. Sequential data input for the serial port. One of two capacitors used to generate the ideal commutation points from the back-EMF zero crossing points.
12 13 14 15 16 17 18-19 20 21 22 23 24
CRES FILTER SECTOR DATA LOGIC SUPPLY OSCILLATOR DATA OUT GROUND RESET CHIP SELECT CLOCK DATA IN CD1
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