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Details, datasheet, quote on part number:A3959SLB-T
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Datasheet text preview:
3959
A3959SLB (SOIC)
CHARGE PUMP
DMOS FULL-BRIDGE PWM MOTOR DRIVER
Designed for pulse-width modulated (PWM) current control of dc motors, the A3959SB, A3959SLB, and A3959SLP are capable of output currents to ±3 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be adjusted via control inputs to operate in slow, fast, and mixed current-decay modes. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM-control signals. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of supply and charge pump, and crossover-current protection. Special power-up sequencing is not required. The A3959SB/SLB/SLP is a choice of three power packages, a 24-pin plastic DIP with a copper batwing tab (package suffix `B'), a 24-lead plastic SOIC with a copper batwing tab (package suffix `LB'), and a thin (<1.2 mm) 28-lead plastic TSSOP with an exposed thermal pad (suffix `LP'). In all cases, the power tab is at ground potential and needs no electrical isolation. Each package is available in a lead-
Data Sheet 29319.37E
CP CP2 CP1 PHASE ROSC GROUND GROUND LOGIC SUPPLY ENABLE PFD2 BLANK PFD1
1 2 3 4 5
24 23 NC 22 21 VBB 20 19 18
VREG SLEEP NO CONNECTION OUTB LOAD SUPPLY GROUND GROUND SENSE OUTA NO CONNECTION EXT MODE REF
Dwg. PP-069-4
6 7 8 9 9 V DD
LOGIC
17 16
PWM TIMER
10 11 12
NC
15 14
÷10
13
Note that the A3959SLB(SOIC), A3959SB (DIP), and A3959SLP (TSSOP) do not share a common terminal assignment.
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB ....... 50 V Output Current, IOUT (Repetitive) .. ±3.0 A (Peak, <3 µs) .. ±6.0 A Logic Supply Voltage, VDD ..... 7.0 V Logic Input Voltage Range, VIN (Continuous) ... -0.3 V to VDD + 0.3 V (tw <30 ns) ...... -1.0 V to VDD + 1.0 V Sense Voltage, VS (Continuous) ..... 0.5 V (tw <3 µs) .......... 2.5 V Reference Voltage, VREF .... VDD Package Power Dissipation (TA = 25°C), PD A3959SB ....... 3.3 W* A3959SLB ..... 2.5 W* A3959SLP ..... 3.1 W* Operating Temp. Range, TA .... -20°C to +85°C Junction Temperature, TJ ............ +150°C Storage Temp. Range, TS ..... -55°C to +150°C Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C.
free version (100% matte tin leadframe). FEATURES
s s s s s s s ±3 A, 50 V Output Rating Low rDS(on) Outputs (270 m, Typical) Mixed, Fast, and Slow Current-Decay Modes Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal-Shutdown Circuitry Crossover-Current Protection Internal Oscillator for Digital PWM Timing
Package 24-pin batwing DIP 24-pin batwing DIP; Lead-free 24-lead batwing SOIC 24-lead batwing SOIC; Lead-free 28-lead thin shrink SOIC 28-lead thin shrink SOIC; Lead-free RJA* 38°C/W 38°C/W 50°C/W 50°C/W 40°C/W 40°C/W R JT 6°C/W 6°C/W 6°C/W 6°C/W -- --
Always order by complete part number:
Part Number A3959SB A3959SB-T A3959SLB A3959SLB-T A3959SLP A3959SLP-T
* Double-sided board, one square inch copper each side. See also, Layout, page 7.
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
VDD LOGIC SUPPLY
CHARGE PUMP BANDGAP VDD CREG TSD
VBB
+
CP1 CP2
LOAD SUPPLY BANDGAP REGULATOR VREG
UNDERVOLTAGE & FAULT DETECT
CHARGE PUMP
SLEEP EXT MODE PHASE ENABLE CONTROL LOGIC
GATE DRIVE
CP
OUTA
OUTB SENSE
ZERO CURRENT DETECT
TO VDD BLANK PFD1 PFD2 ROSC OSC
CURRENT SENSE
CS RS
PWM TIMER
REFERENCE BUFFER & ÷10
REF
VREF
Dwg. FP-048-2A
C P2 CP1 PHASE ROSC GROUND GROUND GROUND GROUND LOGIC SUPPLY ENABLE PFD2 BLANK
1 2 3 4 5
CHARGE PUMP
24 23 22 21 VBB 20 19 18 17
CP VREG SLEEP OUTB LOAD SUPPLY GROUND GROUND SENSE OUTA EXT MODE REF PFD1
Dwg. PP-069-5A
A3959SB (DIP)
Note that the A3959SLB (SOIC), A3959SB (DIP), and A3959SLP (TSSOP) do not share a common terminal assignment.
6 7 8 9 9 10 11 12 V DD
LOGIC
16 15
÷ 10
PWM TIMER
14 13
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2001, 2003 Allegro MicroSystems, Inc.
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise)
Limits Characteristics Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Crossover Delay Body Diode Forward Voltage Load Supply Current VF I BB Source diode, IF = -3 A Sink diode, IF = 3 A fPWM < 50 kHz Charge pump on, outputs disabled Sleep Mode Control Logic Logic Supply Voltage Range Logic Input Voltage Logic Input Current (all inputs except ENABLE) ENABLE Input Current Internal OSC frequency Reference Input Volt. Range Reference Input Current Comparator Input Offset Volt. VD D VI N ( 1 ) VIN(0) I IN(1) I IN(0) I IN(1) I IN(0) fOSC VREF IREF V IO VIN = 2.0 V VIN = 0.8 V VIN = 2.0 V VIN = 0.8 V ROSC shorted to GROUND ROSC = 51 k Operating VREF = VDD VREF = 0 V Operating 4.5 2.0 3.25 3.65 0.0 5.0 <1.0 <-2.0 40 16 4.25 4.25 ± 5.0 5.5 0.8 20 -20 100 40 5.25 4.85 V DD ± 1.0 V V V µA µA µA µA MHz MHz V µA mV V BB I DSS rDS(on) Operating During sleep mode VOUT = VBB VOUT = 0 V Source driver, IOUT = -3 A Sink driver, IOUT = 3 A 9.5 0 300 <1.0 <-1.0 270 270 600 4.0 2.0 50 50 20 -20 300 300 1000 1.6 1.6 7.0 5.0 20 V V µA µA m m ns V V mA mA µA Symbol Test Conditions Min. Typ. Max. Units
Continued next page ...
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3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise), continued.
Limits Characteristics Control Logic Reference Divider Ratio Gm Error (Note 3) Propagation Delay Times t pd EGm VREF = VDD VREF = 0.5 V 0.5 Ein to 0.9 Eout: PWM change to source on PWM change to source off PWM change to sink on PWM change to sink off 600 50 600 50 I n c r e a s i n g V DD fPWM < 50 kHz Sleep Mode 3.90 0.05 10 750 150 750 100 165 15 4.2 0.10 6.0 ± 4.0 ± 14 1200 350 1200 150 4.45 10 2.0 % % ns ns ns ns °C °C V V mA mA Symbol Test Conditions Min. Typ. Max. Units
Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current
TJ TJ UVLO UVLO I DD
NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. Gm error = ([VREF/10] VSENSE)/(VREF/10) where VSENSE = ITRIP·RS.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 µF capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The charge pump is used to generate a gate-supply voltage greater than VBB to drive the sourceside DMOS gates. A 0.22 µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 µF ceramic capacitor should be connected between CP and VBB to act as a reservoir to operate the high-side DMOS devices. The CP voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled. PHASE Logic. The PHASE input terminal determines if the device is operating in the "forward" or "reverse" state. PHASE 0 1 OUTA Low High OUTB High Low EXT MODE Logic. When using external PWM current control, the EXT MODE input determines the current path during the chopped cycle. With EXT MODE low, fast decay mode, the opposite pair of selected outputs will be enabled during the off cycle. With EXT MODE high, slow decay mode, both sink drivers are on with ENABLE low. EXT MODE 0 1 Decay Fast Slow
Current Regulation. Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the DMOS H bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (RS) and the applied analog reference voltage (VREF): ITRIP = VREF/10RS At the trip point, the sense comparator resets the sourceenable latch, turning off the source driver. The load inductance then causes the current to recirculate for the fixed off-time period. The current path during recirculation is determined by the configuration of slow/ mixed/fast current-decay mode via PFD1 and PFD2. Oscillator. The PWM timer is based on an internal oscillator set by a resistor connected from the ROSC terminal to VDD. Typical value of 4 MHz is set with a 51 k resistor. The allowable range of the resistor is from 20 k to 100 k. fOSC = 204 x 109/ROSC. If ROSC is not pulled up to VDD, it must be shorted to ground. Fixed Off Time. The A3959 is set for a fixed off time of 96 cycles of the internal oscillator, typically 24 µs with a 4 MHz oscillator.
ENABLE Logic. The ENABLE input terminal allows external PWM. ENABLE high turns on the selected sinksource pair. ENABLE low switches off the source driver or the source and sink driver, depending on EXT MODE, and the load current decays. If ENABLE is kept high, the current will rise until it reaches the level set by the internal current-control circuit. ENABLE 0 1 Outputs Chopped On
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