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Details, datasheet, quote on part number:A3961SB
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Datasheet text preview:
3961 DUAL FULL-BRIDGE PWM MOTOR DRIVER
3961
Designed for pulse-width modulated (PWM) current control of bipolar stepper motors, the A3961S-- is capable of continuous output currents to ±800 mA and operating voltages to 45 V. Internal fixed off-time PWM current-control circuitry can be used to regulate the maximum load current to a desired value. An internal precision voltage reference is provided to improve motor peak current control accuracy. The peak load current limit is set by the user's selection of an external resistor divider and current-sensing resistors. The fixed off-time pulse duration is set by user-selected external RC timing networks. The capacitor in the RC timing network also determines a user-selectable blanking window that prevents false triggering of the PWM current control circuitry during switching transitions. This eliminates the need for two external RC filter networks on the current-sensing comparator inputs.
Data Sheet 29319.26
DUAL FULL-BRIDGE PWM MOTOR DRIVER
OUT B 1 1 E1 2
24 23
OUT B 2 E2
Note the A3961SB (DIP) and the A3961SLB (SOIC) are electrically identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB . . . . . . . . . . 45 V Output Current, IOUT . . . . . . . . . . ±800 mA* Logic Supply Voltage, VCC . . . . . . . . . 7.0 V Logic Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VCC + 0.3 V Sense Voltage, VSENSE . . . . . . . . . . . . 1.0 V Reference Output Current, IREF OUT . . . . . . . . . . . . . . . . . . . 1.0 mA Package Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . . . -20°C to +85°C Junction Temperature, TJ . . . . . . . +150°C Storage Temperature Range, TS . . . . . . . . . . . . . . . . -55°C to +150°C
* Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated but should be avoided.
T C UY DL ON RO PE DC EN UE IN ER TF NE OR CR IS O DF --
SENSE 1 3 OUT1A 4 VBB1 5
22
SENSE 2
21
OUT A 2 V BB2
20
GROUND 6
19
GROUND
GROUND 7 VREFOUT 8 VREFIN 9
18
GROUND
17
I FULL/PD
16
V CC
RC1 10
15 RC 2
PHASE1 11
14 PHASE 2
ENABLE1 12
13 ENABLE 2
For each bridge the PHASE input controls load current polarity by selecting the appropriate source and sink driver pair. For each bridge the ENABLE input, when held high, disables the output drivers. Special power-up sequencing is not required. Internal circuit protection includes thermal shutdown with hysteresis, transient-suppression diodes, and crossover-current protection. The A3961S-- is supplied in a choice of two power packages: 24-pin dual-in-line plastic package with copper heat-sink tabs and 24-lead plastic SOIC with copper heat-sink tabs. In both packages the power tab is at ground potential and needs no electrical isolation.
FEATURES
s s s s s s s
±800 mA Continuous Output Current Rating 45 V Output Voltage Rating Internal PWM Current Control, Saturated Sink Drivers Internally Generated Precision 2.5 V Reference Internal Transient-Suppression Diodes Internal Thermal-Shutdown Circuitry Crossover-Current Protection, UVLO Protection
Always order by complete part number:
PART NUMBER A3961SB A3961SLB PACKAGE 24-Pin DIP 24-Lead SOIC
RJA 40°C/W 55°C/W
RJT 6°C/W 6°C/W
3961 DUAL FULL-BRIDGE PWM MOTOR DRIVER
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 5
RJT = 6.0°C/W
TRUTH TABLE
ENABLE PHASE X H L OUTA Off H L OUTB Off L H
4
3
SUFFIX 'B', R JA = 40°C/W
H L L
2
1
X = Irrelevant
SUFFIX 'LB', R JA = 55°C/W
0 25 50 75 100 TEMPERATURE IN °C 125 150
Dwg. GP-049A
FUNCTIONAL BLOCK DIAGRAM AND TYPICAL BIPOLAR STEPPER MOTOR APPLICATION
MOTOR SUPPLY 2 MOTOR SUPPLY 1 C BB V BB1 LOGIC SUPPLY C cc V cc GND C BB2
V BB2
OUT 1A OUT 1B
OUT 2A OUT 2B
ENABLE 1 PHASE 1 CONTROL LOGIC AND LEVEL SHIFT BLANKING TIME AND SOURCE DRIVER T OFF CONTROL UVLO AND TSD VOLTAGE REFERENCE CONTROL LOGIC AND LEVEL SHIFT BLANKING TIME AND SOURCE DRIVER T OFF CONTROL
ENABLE 2 PHASE 2
RC1
+ _
+ _
RC 2
SENSE 1 RT1 CT1
E1
I FULL/PD REF OUT R1
REFIN R2
E2 RS2
SENSE 2 CT2 RT2
E2
RS1
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright ©1995, 1996, Allegro MicroSystems, Inc.
3961 DUAL FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 45 V, VCC = 4.75 V to 5.25 V, VSENSE = 0 V, 30 k & 1000 pF RC to Ground (unless noted otherwise)
Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Drivers
Load Supply Voltage Range Output Leakage Current VBB ICEX Operating, IOUT = ±800 mA, L = 3 mH VOUT = VBB VOUT = 0 V Output Saturation Voltage VCE(SAT) Source Driver, IOUT = -500 mA Source Driver, IOUT = -750 mA Source Driver, IOUT = -800 mA Sink Driver, IOUT = +500 mA Sink Driver, IOUT = +750 mA Sink Driver, IOUT = +800 mA Clamp Diode Forward Voltage (Sink or Source) VF IF = 500 mA IF = 750 mA IF = 800 mA Motor Supply Current (No Load) IBB(ON) IBB(OFF) VENABLE = 0.8 V VENABLE = 2.4 V 5.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- <1.0 <-1.0 1.0 1.1 -- 0.3 0.5 -- 1.1 1.3 -- 5.0 5.0 45 50 -50 1.2 1.3 1.4 0.6 0.9 1.0 1.4 1.6 1.7 7.0 7.0 V µA µA V V V V V V V V V mA mA
Control Logic
Logic Supply Voltage Range Logic Input Voltage VCC VIN(1) VIN(0) Logic Input Current IIN(1) IIN(0) Reference Output Voltage VREF OUT VIN = 2.4 V VIN = 0.8 V VCC = 5.0 V, IREF OUT = 90 to 900 µA: IFULL/PD = LOW IFULL/PD = HIGH 2.45 1.49 2.50 1.67 2.55 1.84 V V Operating 4.75 2.4 -- -- -- -- -- -- <1.0 <-2.0 5.25 -- 0.8 20 -200 V V V µA µA
Continued next page...
3961 DUAL FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 45 V, VCC = 4.75 V to 5.25 V, VSENSE = 0 V, 30 kW & 1000 pF RC to Ground (unless noted otherwise) (cont.)
Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units
Control Logic (Continued)
Reference Output Current Ref. Input Offset Current Comparator Input Offset Volt. Comparator Input Volt. Range PWM RC Fixed Off-time PWM Propagation Delay Time PWM Minimum On Time Propagation Delay Times I REF OUT IO S VIO VREF tOFF RC tP W M tON(min) tpd 3 k RD = R1 + R2 15 k VREF IN = 1 V VREF = 0 V Operating CT = 1000 pF, R T = 30 k Comparator Trip to Source OFF CT = 1000 pF ± 5%, RT 15 k, V CC = 5 V IOUT = ±800 mA, 50% to 90%: ENABLE ON to Source ON ENABLE OFF to Source OFF ENABLE ON to Sink ON ENABLE OFF to Sink OFF PHASE Change to Sink ON PHASE Change to Source ON PHASE Change to Sink OFF PHASE Change to Source OFF Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Disable Threshold UVLO Hysterisis Logic Supply Current ICC(ON) ICC(OFF) Logic Supply Current Temperature Coefficient ICC(ON) VENABLE1 = VENABLE2 = 0.8 V VENABLE1 = VENABLE2 = 2.4 V VENABLE1 = VENABLE2 = 0.8 V TJ TJ -- -- -- -- -- -- -- -- -- -- 2.5 0.7 -- -- -- 3.2 1.2 3.2 0.7 3.2 3.2 0.7 1.2 165 15 2.7 0.9 65 11 0.18 -- -- -- -- -- -- -- -- -- -- 2.9 1.1 85 15 -- mA/°C µs µs µs µs µs µs µs µs °C °C V V mA 90 -2.5 -5.0 -0.3 27 -- -- -- 0 0 -- 30 1.2 2.5 900 1.0 5.0 1.0 33 2.0 3.6 µA µA mV V µs µs µs
NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3961 DUAL FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3961S-- contains a fixed off-time pulse-width modulated (PWM) currentcontrol circuit that can be used to limit the load current to a desired value. The peak value of the current limiting (ITRIP) is set by the selection of an external current-sensing resistor (RS ) and reference input voltage (VREF IN). The internal circuitry compares the voltage across the external sense resistor to the voltage on the reference input terminal (VREF IN), resulting in a transconductance function approximated by: ITRIP VREF IN RS The reference input voltage is typically set with a resistor divider from VREF OUT. The value of VREF OUT can be switched from a nominal value of 2.5 V to 1.67 V by applying a low or high logic signal respectively to the I FULL/PD terminal. To ensure proper operation of the voltage reference, the resistor divider (RD = R1+R2) should have an impedance of 3 k to 15 k. Within this range, a low impedance will minimize the effect of the REF IN input offset current. The current-control circuitry limits the load current as follows: when the load current reaches ITRIP, the comparator resets a latch that turns off the selected source driver. The load inductance causes the current to recirculate through the sink driver and flyback diode. For each bridge, the user selects an external resistor (RT) and capacitor (CT) to determine the time period (tOFF = RTCT) during which the source driver remains disabled (see "RC Fixed Off-time" below). The range of recommended values for CT and RT are 1000 pF to 1500 pF and 15 k to 100 k respectively. For optimal load current regulation, CT is normally set to 1000 pF (see "Load Current Regulation" below). At the end of the RC interval, the source driver is enabled allowing the load current to increase again. The PWM cycle repeats, maintaining the peak load current at the desired value. internal current-control circuitry (or by the PHASE or ENABLE inputs). The comparator output is blanked to prevent false over-current detections due to reverserecovery currents of the clamp diodes, and/or switching transients related to distributed capacitance in the load. During internal PWM operation, at the end of the tOFF time, the comparator's output is blanked and CT begins to be charged from approximately 1.1 volts by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on CT reaches approximately 3.0 volts. When a transition of the PHASE input occurs, CT is discharged to near ground during the crossover delay time (The crossover delay time is present to prevent simultaneous conduction of the source and sink drivers). After the crossover delay, CT is charged by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on C T reaches approximately 3.0 volts. When the device is disabled, via the ENABLE input, CT is discharged to near ground. When the device is re-enabled, CT is charged by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on CT reaches approximately 3.0 volts. The minimum recommended value for CT is 1000 pF. This value ensures that the blanking time is sufficient to avoid false trips of the comparator under normal operating conditions. For optimal regulation of the load current, the above value for CT is recommended and the value of RT can be sized to determine tOFF. For more information regarding load current regulation, see below.
Load Current Regulation. Because the device operates in a slow decay mode (2-quadrant PWM mode), there is a limit to the lowest level that the PWM current control circuitry can regulate load current. The limitation is due to the minimum PWM duty cycle, which is a function of the userselected value of tOFF and the minimum on-time pulse tON(min)max that occurs each time the PWM latch is reset. RC BLANKING. In addition to determining the fixed offIf the motor is not rotating, as in the case of a stepper motime of the PWM control circuit, the CT component sets the tor in hold/detent mode, a brush dc motor when stalled or comparator blanking time. This function blanks the output at startup, the worst case value of current regulation can of the comparator when the outputs are switched by the be approximated by: [(VBB - V SAT(SOURCE+SINK)) tON(min) max] (1.05 (VSAT(SINK) + VF) tOFF) I AVG 1.05 (tON(min) max + tOFF) RLOAD
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