|
Details, datasheet, quote on part number:A3968SA
| |
Datasheet text preview:
3968
A3968SLB
OUT1A INPUT1A INPUT1B GROUND SENSE 1 OUT 1B LOAD SUPPLY REFERENCE 1 V 2 3 4 5 6 V 7 8 V
BB BB
DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
The A3968SA and A3968SLB are designed to bidirectionally control two dc motors. Each device includes two H-bridges capable of continuous output currents of ±650 mA and operating voltages to 30 V. Motor winding current can be controlled by the internal fixed-frequency, pulse-width modulated (PWM), current-control circuitry. The peak load current limit is set by the user's selection of a reference voltage and current-sensing resistors. Except for package style and pinout, the two devices are identical. The fixed-frequency pulse duration is set by a user-selected external RC timing network. The capacitor in the RC timing network also determines a user-selectable blanking window that prevents false triggering of the PWM current-control circuitry during switching transitions. To reduce on-chip power dissipation, the H-bridge power outputs have been optimized for low saturation voltages. The sink drivers feature Allegro's patented SatlingtonTM output structure. The Satlington outputs combine the low voltage drop of a saturated transistor and the high peak current capability of a Darlington. For each bridge, the INPUTA and INPUTB terminals determine the load current polarity by enabling the appropriate source and sink driver pair. When a logic low is applied to both INPUTs of a bridge, the braking function is enabled. In brake mode, both source drivers are turned OFF and both sink drivers are turned ON, thereby dynamically braking the motor. When a logic high is applied to both INPUTs of a bridge, all output drivers are disabled. Special power-up sequencing is not required. Internal circuit protection includes thermal shutdown with hysteresis, ground-clamp and flyback diodes, and crossover-current protection. The A3968SA is supplied in a 16-pin dual in-line plastic package. The A3968SLB is supplied in a 16-lead plastic SOIC with copper heat sink tabs. The power tab is at ground potential and needs no electrical isolation.
Data Sheet 29319.29*
16 15 14 LOGIC LOGIC 13 12 11 V CC RC 10 9
OUT 2A INPUT2A INPUT2B GROUND SENSE 2 OUT 2B LOGIC SUPPLY RC
REF
Dwg. PP-066
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB .......... 30 V Output Current, IOUT (peak) .......... ±750 mA (continuous) ...... ±650 mA Logic Supply Voltage, VCC ........ 7.0 V Input Voltage, Vin ..... -0.3 V to VCC + 0.3 V Sense Voltage, VS ........ 1.0 V Package Power Dissipation (TA = 25°C), PD A3968SA .. 2.08 W* A3968SLB ......... 1.87 W* Operating Temperature Range, TA .. -20°C to +85°C Junction Temperature, TJ ....... +150°C Storage Temperature Range, TS ......... -55°C to +150°C
Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. * Per SEMI G42-88 Specification, Thermal Test Board Standardization for Measuring Junctionto-Ambient Thermal Resistance of Semiconductor P a c k a g e s.
FEATURES
s s s s s s s s s ±650 mA Continuous Output Current 30 V Output Voltage Rating Internal Fixed-Frequency PWM Current Control SatlingtonTM Sink Drivers Brake Mode User-Selectable Blanking Window Internal Ground-Clamp & Flyback Diodes Internal Thermal-Shutdown Circuitry Crossover-Current Protection and UVLO Protection
Always order by complete part number:
Part Number A3968SA A3968SLB Package 16-pin DIP 16-lead batwing SOIC RJA 6 0° C / W 6 7° C / W RJC 3 8° C / W 6° C / W RJT
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
FUNCTIONAL BLOCK DIAGRAM
(one-half of circuit shown)
LOGIC SUPPLY LOAD SUPPLY OUTA OUTB
INPUTA
V CC
+
V BB
UVLO & TSD
INPUTB
CONTROL LOGIC
SOURCE ENABLE
PWM LATCH R Q S
BLANKING GATE
CURRENT-SENSE COMPARATOR
SENSE
TO OTHER BRIDGE ÷4
+
TO OTHER BRIDGE
GROUND RC
OSC TO OTHER BRIDGE
RS
RT
CT
REFERENCE
Dwg. FP-036-4
A3968SA
SENSE 1 OUT 1B LOAD SUPPLY REFERENCE RC LOGIC SUPPLY OUT 2B SENSE 2 1 16 INPUT1B INPUT1A OUT 1A GROUND GROUND OUT 2A INPUT 2A INPUT 2B
TRUTH TABLE
INPUTA L L H H INPUTB L H L H OUTA L L H Z OUTB L H L Z Description Brake mode Forward Reverse Disable
2 3 4 5 6 7 8 V REF RC V
LOGIC
15 14
V BB
13 12 11
Z = High impedance
CC
LOGIC
10 9
Dwg. PP-066-3
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright ' 1998, Allegro MicroSystems, Inc.
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V, VS = 0 V, 56 k & 680 pF RC to Ground (unless noted otherwise)
Limits Characteristic Output Drivers
Load Supply Voltage Range Output Leakage Current V BB I CEX Operating, IOUT = ±650 mA, L = 3 mH VOUT = 30 V VOUT = 0 V Output Saturation Voltage V CE(SAT) Source Driver, IOUT = -400 mA Source Driver, IOUT = -650 mA Sink Driver, IOUT = +400 mA, VS = 0.5 V Sink Driver, IOUT = +650 mA, VS = 0.5 V Clamp Diode Forward Voltage VF IF = 400 mA IF = 650 mA Motor Supply Current (No Load) IB B ( O N ) IB B ( O F F ) Both bridges ON (forward or reverse) All INPUTs = 2.4 V V CC <1.0 <-1.0 1.7 1.8 0.3 0.4 1.1 1.4 3.0 <1.0 30 50 -50 2.0 2.1 0.5 1.3 1.4 1.6 5.0 200 V µA µA V V V V V V mA µA
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Control Logic
Logic Supply Voltage Range Logic Input Voltage VCC V IN(1) V IN(0) Logic Input Current II N ( 1 ) II N ( 0 ) Reference Input Volt. Range Reference Input Current Reference Divider Ratio Current-Sense Comparator Input Offset Voltage Current-Sense Comparator Input Voltage Range Sense-Current Offset VREF IR E F VREF/VTRIP VIO VS IS O VREF = 0.1 V Operating IS -- OUT, 50 mA IOUT 650 mA I VIN = 2.4 V VIN = 0.8 V Operating 0.1 -2.5 3.8 -6.0 -0.3 12 18 <1.0 <-20 -- 0 4.0 0 Operating 4.75 2.4 0.8 20 -200 2.0 1.0 4.2 6.0 1.0 24 mV V mA 5.50 V V V µA µA V µA
NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.
www.allegromicro.com
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V, VS = 0 V, 56 k & 680 pF RC to Ground (unless noted otherwise) (cont.)
Limits Characteristic Control Logic (continued)
PWM RC Frequency PWM Propagation Delay Time f osc tP W M CT = 680 pF, RT = 56 k Comparator Trip to Source OFF Cycle Reset to Source ON Cross-Over Dead Time Propagation Delay Times t codt tp d 1 k Load to 25 V IOUT = ±650 mA, 50% to 90%: Disable OFF to Source ON Disable ON to Source OFF Disable OFF to Sink ON Disable ON to Sink OFF Brake Enable to Sink ON Brake Enable to Source OFF 0.2 22.9 25.4 1.0 0.8 1.8 100 500 200 200 2200 200 165 15 I n c r e a s i n g V CC 0.1 Both bridges ON (forward or reverse) All INPUTs = 2.4 V All INPUTs = 0.8 V 4.1 0.6 50 9.0 95 4.6 27.9 1.4 1.2 3.0 kHz µs µs µs ns ns ns ns ns ns °C °C V V mA mA mA
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current
TJ T J V T(UVLO)+ V T(UVLO)hys IC C ( O N ) IC C ( O F F ) I CC(BRAKE)
NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3968SA and A3968SLB dual H-bridges are designed to bidirectionally control two dc motors. An internal fixed-frequency PWM current-control circuit controls the load current in each motor. The current-control circuitry works as follows: when the outputs of the H-bridge are turned on, current increases in the motor winding. The load current is sensed by the current-control comparator via an external sense resistor (RS). Load current continues to increase until it reaches the predetermined value, set by the selection of external current-sensing resistors and reference input voltage (VREF) according to the equation: ITRIP = IOUT + ISO = VREF/(4 RS) where ISO is the sense-current error (typically 18 mA) due to the base-drive current of the sink driver transistor. At the trip point, the comparator resets the sourceenable latch, turning off the source driver of that H-bridge. The source turn off of one H-bridge is independent of the other H-bridge. Load inductance causes the current to recirculate through the sink driver and ground-clamp diode. The current decreases until the internal clock oscillator sets the source-enable latches of both H-bridges, turning on the source drivers of both bridges. Load current increases again, and the cycle is repeated. The frequency of the internal clock oscillator is set by
INPUT A
the external timing components RTCT. The frequency can be approximately calculated as: fosc = 1/(RT CT + tblank) where tblank is defined below. The range of recommended values for RT and CT are 20 k to 100 k and 470 pF to 1000 pF respectively. Nominal values of 56 k and 680 pF result in a clock frequency of 25.4 kHz. Current-Sense Comparator Blanking. When the source driver is turned on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the current-control comparator output is blanked for a short period of time when the source driver is turned on. The blanking time is set by the timing component CT according to the equation: tblank = 1900 CT (µs). A nominal CT value of 680 pF will give a blanking time of 1.3 µs. The current-control comparator is also blanked when the load current changes polarity (direction or phase change). This internally generated blank time is approximately 1.8 µs.
INPUT B
V BB
"FORWARD" BRIDGE ON ALL OFF "REVERSE"
+ I OUTB 0
BRIDGE ON SOURCE OFF
SOURCE OFF
BRIDGE ON td
I TRIP
ALL OFF
RTC T
INTERNAL OSCILLATOR
t
blank
RS
Dwg. WM-003-3
Dwg. EP-006-16
www.allegromicro.com
|
|
