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Details, datasheet, quote on part number:A3971
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Datasheet text preview:
3971
ADVANCE INFORMATION
(Subject to change without notice) May 2, 2000
DUAL DMOS FULL-BRIDGE DRIVER
Designed to interface between external PWM control logic and inductive loads such as relays, solenoids, dc motors, or stepper motors, each full bridge can operate with output currents to ±2.5 A and operating voltages to 50 V. Low rDS(on) DMOS output drivers provide low power dissipation during PWM operation. Internal charge pump circuitry is used to create a boosted voltage to fully enhance the high-side DMOS switches. Three TTL-compatible logic-input terminals per bridge allow flexibility in configuring PWM control. Internal circuit protection includes thermal shutdown with hysteresis, and crossover-current protection. Special power -up sequencing is not required. The A3971SLB is supplied in a 24-lead plastic SOIC with a copper batwing tab. The power tab is at ground potential and needs no electrical isolation.
Data Sheet 29319.32
NO CONNECTION LOGIC GROUND S10 OUT1A LOAD SUPPLY1 GROUND GROUND SENSE1 OUT1B S11 PWM1 CP1
1 2 3 4 5 6 7 8 9 9 10 11 12
NC
VDD
24 23 22 21 20 19 18 17 16
LOGIC SUPPLY PWM2 S20 OUT2A LOAD SUPPLY2 GROUND GROUND SENSE2 OUT2B S21
VBB1
VBB2
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB ....... 50 V Output Current, IOUT Transient (<500 ns) .......... ±5 A Logic Supply Voltage, VDD ........... 7.0 V Sense Voltage, VSENSE .... 0.5 V Logic Input Voltage Range, VIN ......... -0.3 V to VDD + 0.3 V High-Side Gate Voltage .. VBB + 8 V Package Power Dissipation, PD ............ 2.2 W Operating Temperature Range, TA ..... -20°C to +85°C Junction Temperature, TJ .... +150°C Storage Temperature Range, TS ... -55°C to +150°C
Output duty cycle, ambient temperature, and heat sinking may limit current rating. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150 °C.
ct u dy ro nl PO de ec un in re t n fe oe cR is r Do F
15 14 VCP CHARGE PUMP 13 CP2
Dwg. PP-069-2
LOGIC
LOGIC
FEATURES
s ±2.5 A Load Current Capability per Bridge
s Parallel Outputs for 5 A Load-Current Capability s Low rDS(on) Outputs Typically 325 m source, 175 m sink
s Synchronous Rectification via Control Logic s Internal Undervoltage Monitor s Crossover-Current Protection
s Source Connections for External Current Sensing s Thermal Shutdown Circuitry
Always order by complete part number: A3971SLB .
3971 DUAL DMOS FULL-BRIDGE DRIVER
FUNCTIONAL BLOCK DIAGRAM
0.22 µF/100 V
LOGIC SUPPLY VDD 24 VR F E
CP2 13 12
CP1 V CP LOAD SUPPLY
VOLTAGE REFERENCE
LOW SIDE SUPPLY
CHARGE PUMP
14
0.22 µF 50 V
20
V BB2
DMOS H-BRIDGE
V CP
UVLO & THERMAL SHUTDOWN
21
OUT 2A
16
OUT 2B
S10 3 S11 10 PWM1 11
BRIDGE 1 CONTROL LOGIC GATE DRIVE DMOS H-BRIDGE
17
SENSE2
RS , CS (OPTIONAL)
5 V BB1
S20 22 S 21 15 PWM2 23
BRIDGE 2 CONTROL LOGIC
4
OUT1A
9
OUT1B
LGND
2
SENSE 1 8 6 GROUND 7 18 19
RS , CS (OPTIONAL)
Dwg. FP-050
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, 2002 Allegro MicroSystems, Inc.
3971 DUAL DMOS FULL-BRIDGE DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V (unless otherwise noted).
Limits Characteristic Load Supply Voltage Range Logic Supply Voltage Range Load Supply Current Logic Supply Current Output Drivers Output Leakage Current I DSS rDS(on) VF V CP VIN(0) VIN(1) Logic Input Current I IN(0) I IN(1) Propagation Delay Time t PD V IN = 0 V VIN = 5.0 V 50% to 90%: PWM change to source off PWM change to sink off PWM change to source on PWM change to sink on Disable to source on Disable to sink on Thermal Shutdown Temperature Thermal Shutdown Hysteresis UVLO Threshold UVLO Hysteresis TJ TJ V UVLO V U V L O I n c r e a s i n g VD D -- -- -- -- -- -- -- -- 3.9 -- 50 60 565 665 150 250 165 15 4.15 0.15 -- -- -- -- -- -- -- -- 4.4 -- ns ns ns ns ns ns °C °C V V V OUT = V BB V OUT = 0 V Output ON Resistance High-side switch, IOUT = -2.5 A Low-side switch, IOUT = 2.5 A Body Diode Forward Voltage Source diode, IF = 2.5 A Sink diode, IF = 2.5 A High-Side Gate Voltage Control Logic Logic Input Voltage -- 2.0 -- -- -- -- <1.0 20 0.8 -- -5.0 50 V V µA µA C = 0.22 µF, reference VBB -- -- -- -- -- -- 6.0 <1.0 <-1.0 325 175 1.2 1.0 6.5 20 -20 375 200 -- -- 7.0 µA mA m m V V V Symbol VBB V DD I BB IDD Test Conditions Operating Operating Operating, each supply, no load Operating Min. 10 4.5 -- -- Typ. -- 5.0 -- -- Max. 50 5.5 3.0 5.0 Units V V mA mA
NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.
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3971 DUAL DMOS FULL-BRIDGE DRIVER
Logic Truth Table
P W Mx X 0 0 0 1 1 1 S x0 0 0 1 1 0 1 1 S x1 0 1 0 1 1 1 0 O U T xA Z L H L L L L O U T xB Z H L L L L L Function Disable Forward Reverse Synchronous Rectification/ Slow Decay Chop
Terminal List
Terminal 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18, 19 20 21 22 23 24 Name NC LGND S 10 O U T1 A V BB1 GND SENSE 1 O U T1 B S 11 PWM1 CP1 CP2 V CP S 21 OUT2B SENSE 2 GND V BB2 OUT2A S 20 PWM2 V DD Description No (Internal) connection Logic ground Control input, bridge 1 Output A, bridge 1 Load supply voltage, bridge 1 Ground Sense resistor, bridge 1 Output B, bridge 1 Control input, bridge 1 Control input, bridge 1 Charge-pump capacitor Charge-pump capacitor Reservoir capacitor Control input, bridge 2 Output B, bridge 2 Sense resistor, bridge 2 Ground Load supply voltage, bridge 2 Output A, bridge 2 Control input, bridge 2 Control input, bridge 2 Logic supply voltage
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3971 DUAL DMOS FULL-BRIDGE DRIVER
Functional Description
Charge Pump. The DMOS output stage requires a charge pump to bring the high-side gate-source voltage approximately 8 V above the VBB supply. Two external components are required, a pumping capacitor connected between CP1 and CP2 and a reservoir capacitor connected between VBB and VCP. Ceramic 0.22 µF capacitors are recommended. Control Logic. Each bridge is controlled by three TTLcompatible inputs. The inputs are resistively pulled to ground (via 250 k). A crossover-delay circuit protects the outputs from a shoot-thru condition when going from a forward or reverse on state to synchronous rectification/ slow decay chop (both sink drivers on). If the logic is in the DISABLE state and changes to an on state the 415 ns crossover delay does not occur. Protection Circuitry. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VDD, the outputs of the device are disabled until the fault condition is removed. Current Sensing. If external current-sensing circuitry is used, the sense resistor should have an independent ground return to the ground terminal of the device. Due to current transients during switching, a 0.1 µF capacitor should be connected from the sense terminal to the batwing tab connection of the package. This capacitor reduces voltage swings at the terminal due to the fast di/dt, which in turn ensures that the sink driver gate-source voltage stays within the safe operating area. Allegro MicroSystems recommends a value of RS given by: RS = 0.5/ITRIP max. Thermal protection. Circuitry turns off all drivers when the junction temperature reaches 165°C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. If external current sensing is used, the ground side of RS should have an individual path to the ground terminal(s) of the device. This path should be as short as is possible physically and should not have any other components connected to it. The load supply terminal should be decoupled with an electrolytic capacitor ( >47 µF is recommended) placed as close to the device as is possible. Parallel Operation. For high-power applications, the two DMOS full bridges in the A3971 may be connected in parallel as shown below. The current will be shared equally in each full bridge due to the positive temperature coefficient of the DMOS rDS(on).
PWM CONTROL
+5 V 1 2 3 4 NC VDD 24 23 22 21 1550 V VBB1 VBB2
1550 V
LOGIC
LOGIC
47 µF
6 7 8 9 9 10 11 12
19 18 17 16
14 CHARGE PUMP 13
0.22 µF
0.22 µF
Dwg. EP-069
15
www.allegromicro.com
47 µF
+
5
20
+
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