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Details, datasheet, quote on part number:A3974SED
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Datasheet text preview:
3974
LOAD 43 SUPPLY1 SENSE1 OUT1A ENABLE1 GND GND GND NC OUT1B NC NC
DMOS DUAL FULL-BRIDGE PWM MOTOR DRIVER
Designed for pulse-width modulated (PWM) current control of two dc motors, the A3974SED is capable of output currents to ±1.5 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current-decay modes. Independant ENABLE input terminals are provided for use in controlling the speed and torque of each dc motor with externally applied PWM control signals. Synchronous rectification circuitry allows the load current to flow through the low rDS(on) of the DMOS output driver during the current decay. This feature will eliminate the need for external clamp diodes in most applications, saving cost and external component count, while minimizing power dissipation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of VDD and the charge pump, and crossover-current protection. Special power-up sequencing is not required. The A3974SED is supplied in a 44-lead plastic PLCC with four copper batwing tabs for maximum heat dissipation. The power tabs are at ground potential and need no electrical isolation.
41 44 42 40 2 4 6 5 3 1
Data Sheet 29319.35
VBB1 NC STROBE CLOCK 7 39 NC CP2 CP1 CP GND GND GND OSC SLEEP VREG NC
8 9
CHARGE PUMP
SERIAL PORT
38 37 36 35 34 33
PROGRAM PWM TIMER
LOGIC
DATA 10 GND 11 GND 12 GND 13 REF1 14 REF2 15 LOGIC 16 SUPPLY NC 17 VDD
÷ ÷
PROGRAM PWM TIMER LOGIC
32 31 30 29 VBB2
OUT2A 18
NC 20
21
GND 22
23
GND 24
25
ENABLE2 26
NC 19
SENSE2
LOAD SUPPLY2
OUT2B 28
GND
NC 27
Dwg. PP-073
ABSOLUTE MAXIMUM RATINGS at TA = +25°C
Load Supply Voltage, VBB .... 50 V Output Current, IOUT .......... ±1.5 A Logic Supply Voltage, VDD .. 7.0 V Logic Input Voltage Range, VIN Continous .......... -0.3 V to VDD + 0.3 V tW < 30 ns .......... -1.0 V to VDD + 1.0 V Reference Voltage, VREF ......... 3 V Sense Voltage (dc), VS Continous .... 0.5 V tW < 1 µs ...... 2.5 V Package Power Dissipation, PD ......... 3.9 W Operating Temperature Range, TA ........ -20°C to +85°C Junction Temperature, TJ ....... +150°C Storage Temperature Range, TS ...... -55°C to +150°C
Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C.
FEATURES
s ±1.5 A, 50 V Continuous Output Rating s Low rDS(on) DMOS Output Drivers s Programmable Slow, Fast, and Mixed Current-Decay Modes s Serial-Interface Controls Chip Functions s Synchronous Rectification for Low Power Dissipation s Internal UVLO and Thermal Shutdown Circuitry s Crossover-Current Protection s Sleep and Idle Modes
Always order by complete part number: A3974SED .
3974 DMOS DUAL FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
VDD LOGIC SUPPLY
CHARGE PUMP BANDGAP VDD CREG TSD
VBB1
+
CP1 CP2
LOAD SUPPLY1 BANDGAP REGULATOR VREG
UNDERVOLTAGE & FAULT DETECT
CHARGE PUMP
CONTROL LOGIC
CP
PHASE SYNC RECT MODE SYNC RECT DISABLE MODE
OUT1A
ENABLE1
GATE DRIVE
OUT1B SENSE1 CS1
FIXED OFF PROGRAMMABLE BLANK DECAY
ZERO CURRENT DETECT
RS1
PWM TIMER
OSC CLOCK DATA STROBE
CURRENT SENSE
SERIAL PORT
REFERENCE BUFFER & DIVIDER
REF1 LOAD SUPPLY2
VREF VBB2
PROGRAMMABLE PWM TIMER
FIXED OFF BLANK DECAY
CHARGE PUMP
+
ENABLE2
GATE DRIVE
SLEEP MODE
PHASE ENABLE SYNC RECT MODE SYNC RECT DISABLE PWM MODE INT PWM MODE EXT
OUT2A
OUT2B SENSE2
CONTROL LOGIC
TO PWM TIMER
CS2
ZERO CURRENT DETECT
RS2
CURRENT SENSE
REFERENCE BUFFER & DIVIDER
REF2
VREF2
Dwg. FP-048-1
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2001 Allegro MicroSystems, Inc.
3974 DMOS DUAL FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50 kHz (unless otherwise noted).
Characteristic Output Drivers Load Supply Voltage Range VBB Operating During sleep mode Output Leakage Current I DSS V OUT = V BB V OUT = 0 V Output ON Resistance rDS(on) Source driver, IOUT = -1.5 A Sink driver, IOUT = 1.5 A Body Diode Forward Voltage VF Source diode, IF = 1.5 A Sink diode, IF = 1.5 A Load Supply Current I BB fPWM < 50 kHz Charge pump on, outputs disabled Sleep or idle mode Control Logic Logic Supply Voltage Range Logic Input Voltage V DD VIN(1) VIN(0) Logic Input Current (except ENABLE) ENABLE Input Current I IN(1) I IN(0) IEN(1) IEN(0) OSC Input Frequency OSC Input Duty Cycle OSC Input Hysterisis Reference Input Voltage Range f OSC -- VIN V REF Operating VIN = 2.0 V VIN = 0.8 V VEN = 2.0 V VEN = 0.8 V Operating 4.5 2.0 -- -- -- -- -- 2.9 40 200 0 5.0 -- -- <1.0 <1.0 40 16 -- -- -- -- 5.5 -- 0.8 ± 20 ± 20 100 30 6.1 60 400 2.6 V V V µA µA µA µA MHz % mV V 15 0 -- -- -- -- -- -- -- -- -- -- -- <1.0 <-1.0 0.5 0.315 -- -- 4.0 2.0 -- 50 50 20 -20 0.55 0.35 1.2 1.2 7.0 5.0 20 V V µA µA V V mA mA µA Symbol Test Conditions Min. Limits Typ. Max. Units
continued next page ...
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3974 DMOS DUAL FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50 kHz (unless otherwise noted), continued.
Limits Typ. Max. -- ± 10 10 5.0 0 0 0 0 750 150 750 150 600 165 15 4.2 0.10 -- -- -- -- ± 1.0 -- -- -- ± 4.0 ± 14 ± 4.0 ± 10 1000 350 1000 350 1000 -- -- 4.45 -- 10 8.0 1.5 100
Characteristic Control Logic (continued) Reference Input Current Reference Input Offset Voltage Reference Divider Ratio
Symbol I REF VIO VREF/VS
Test Conditions VREF = 2.6 V
Min. -- --
Units µA mV -- -- % % % % ns ns ns ns ns °C °C V V mA mA mA µA
D16 = 1 D16 = 0
-- -- -- -- -- -- 600 50 600 50 300 -- --
Gain (Gm) Error (note 3)
EG
VREF = 2.6 V, D16 = 0 VREF = 0.5 V, D16 = 0 VREF = 2.6 V, D16 = 1 VREF = 0.5 V, D16 = 1
Propagation Delay Time
tpd
50% TO 90%: PWM change to source on PWM change to source off PWM change to sink on PWM change to sink off SR enabled
Crossover Delay Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current
t COD TJ T J V UVLO V U V L O IDD
I n c r e a s i n g VD D
3.9 0.05
fPWM < 50 kHz Outputs off Idle mode (D18 = 1, D19 = 0) Sleep mode (inputs below 0.5 V)
-- -- -- --
NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. EG = [(VREF/Range) - VS]/(VREF/Range).
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3974 DMOS DUAL FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
Serial Interface. The A3974SED is controlled via a 3-wire (clock, data,strobe) serial port. The programmable functions allow maximum flexibility in configuring the PWM to the motor drive requirements. The serial data is written as two 20bit words: 1 bit to select the word and 19 bits of data. The data is clocked in starting with D19. Word 0 Bit Assignments Select Word 0 (D18 = 0) Bit Function D0 Bridge 1 blank time LSB D1 Bridge 1 blank time MSB D2 Bridge 1 off-time LSB D3 Bridge 1 off-time bit 1 D4 Bridge 1 off-time bit 2 D5 Bridge 1 off-time bit 3 D6 Bridge 1 off-time MSB D7 Bridge 1 fast-decay time bit LSB D8 Bridge 1 fast-decay time bit 1 D9 Bridge 1 fast-decay time bit 2 D10 Bridge 1 fast-decay time MSB D11 Bridge 1 sync. rect. control D12 Bridge 1 sync. rect. control D13 Bridge 1 external PWM mode D14 Bridge 1 enable D15 Bridge 1 phase D16 Bridge 1 reference range select D17 Bridge 1 internal PWM mode D18 Word select = 0 D19 Test mode D0 D1 Blank Time. The current-sense comparator is blanked when any output driver is switched on, according to the table below. fosc is the oscillator input frequency. D1 0 0 1 1 D0 0 1 0 1 Blank Time 4 / f OSC 6 / f OSC 1 2 / f OSC 2 4 / f OSC D2 D6 Fixed Off Time. This five-bit word sets the fixed off-time for the internal PWM control circuitry. The off-time is defined by toff =(8 [1 + N]/fOSC) - 1/fOSC where N = 0 .... 31 For example, with an oscillator frequency of 4 MHz, the fixed off-time will be adjustable from 1.75 µs to 63.75 µs in increments of 2 µs. D7 D10 Fast Decay Time. This four-bit word sets the fastdecay portion of the fixed off-time for the internal PWM control circuitry. This will only have impact if mixed-decay mode is selected (via bit D17). For tfd > toff, the device will effectively operate in fast-decay mode. The fast-decay portion is defined by tfd = (8[1 + N]/fOSC] - 1/fOSC where N = 0 .... 15 For example, with an oscillator frequency of 4 MHz, the fastdecay time will be adjustable from 1.75 µs to 31.75 µs in increments of 2 µs. D11 D12 Synchronous Rectification. D12 0 0 1 1 D11 0 1 0 1 Synchronous Rectifier Disabled Low side only Active Passive
The different modes of operation are described in the synchronous rectification section of the functional description. D13 External PWM Decay Mode. This bit determines the current-decay mode when using ENABLE chopping for external PWM current control. D13 0 1 Mode Fast Slow continued next page ...
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