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Details, datasheet, quote on part number:A3977SLP-T
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Datasheet text preview:
3977
A3977xED
(PLCC)
LOAD SUPPLY 1 SENSE 1 ENABLE OUT 1A HOME GND GND GND SLEEP OUT 1B
MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
The A3977xED and A3977xLP are complete microstepping motor drivers with built-in translator. They are designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 35 V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This currentdecay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3977. By simply inputting one pulse on the STEP input the motor will take one step (full, half, quarter, or eighth depending on two logic inputs). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3977 interface is an ideal fit for applications where a complex µP is unavailable or over-burdened. Internal synchronous-rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, under-voltage lockout (UVLO) and crossover-current protection. Special power-up sequencing is not required. The A3977 is supplied in a choice of two power packages, a 44-pin plastic PLCC with copper batwing tabs (suffix ED), and a thin (<1.2 mm), 28pin TSSOP with an exposed thermal pad (suffix LP). The SLP package is available in a lead-free version (100% matte tin leadframe).
Data Sheet 26184.22C
DIR
6
5
4
3
2
1
44
43 VBB1
42
41
40
NC NC PFD
7
CHARGE PUMP
39 NC 38 CP2 37 CP1 36 VCP 35 GND 34 GND 33 GND REG 32 VREG
8 9 PWM TIMER
RC1 10 GND 11 GND 12 GND 13 REF 14 RC2 15 LOGIC SUPPLY 16 NC 17 VBB2 18
OUT 2A TRANSLATOR & CONTROL LOGIC
÷8
31 STEP VDD 30 NC 29 NC
19
MS 2
20
MS1
21
SENSE 2
22
GND
23
GND
24
GND
25
SUPPLY LOAD 2
26
SR
27
RESET
28
OUT 2B
Dwg. PP-075-1
ABSOLUTE MAXIMUM RATINGS at TA = +25°C
Load Supply Voltage, VBB .... 35 V Output Current, IOUT ......... ±2.5 A* Logic Supply Voltage, VDD .. 7.0 V Logic Input Voltage Range, VIN (tw >30 ns) ..... -0.3 V to VDD + 0.3 V (tw <30 ns) .. -1 V to VDD + 1 V Sense Voltage, VSENSE ........ 0.5 V Reference Voltage, VREF ....... VDD Package Power Dissipation, PD ......... See page 3 Operating Temperature Range, TA (A3977Kx) ... -40°C to +125°C (A3977Sx) ..... -20°C to +85°C Junction Temperature, TJ ......... +150°C Storage Temperature Range, TS ....... -55°C to +150°C
* Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C.
FEATURES
±2.5 A, 35 V Output Rating Low rDS(on) Outputs, 0.45 Source, 0.36 Sink Typical Automatic Current Decay Mode Detection/Selection 3.0 V to 5.5 V Logic Supply Voltage Range Mixed, Fast, and Slow Current Decay Modes Home Output Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection
Always order by complete part number:
Part Number A3977KED A3977KLP A3977SED A3977SLP A3977SLP-T Package 44-pin PLCC 28-pin TSSOP 44-pin PLCC 28-pin TSSOP 28-pin TSSOP; Lead-free
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
FUNCTIONAL BLOCK DIAGRAM
LOGIC SUPPLY VDD REF. SUPPLY REF UVLO AND FAULT 2V REGULATOR BANDGAP
VREG
CP2 CHARGE PUMP
CP1 VCP
LOAD SUPPLY
VBB1
DMOS H BRIDGE
DAC +-
SENSE1
VCP
RC1
PWM LATCH BLANKING MIXED DECAY
OUT1A OUT1B
4 STEP
PWM TIMER
M S1 MS2 HOME SLEEP VPFD SR
CONTROL LOGIC
GATE DRIVE
RESET
TRANSLATOR
DIR
SENSE1
DMOS H BRIDGE
VBB2
OUT2A OUT2B
ENABLE PWM TIMER PFD 4
PWM LATCH BLANKING MIXED DECAY
RC2 DAC
+
-
SENSE2
Dwg. FP-050-2
2
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2002, 2003 Allegro MicroSystems, Inc.
3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
A3977xLP
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
(TSSOP)
SENSE1 HOME DIR OUT1A PFD RC1 AGND REF RC2 LOGIC SUPPLY OUT2A MS2 MS1 SENSE2 1 2 3 4 VBB1 28 27 26 25 LOAD SUPPLY1 SLEEP ENABLE OUT1B CP2 CP1 VCP PGND VREG STEP OUT2B RESET SR LOAD SUPPLY2
Dwg. PP-075
5.0
SUFFIX 'LP', RJA = 28°C/W*
4.0
SUFFIX 'ED', RJA = 32°C/W
PWM TIMER
CHARGE PUMP
5 6 7 8 9 10 11 12 13 14
24 23 22 21
3.0
SUFFIX 'LP', RJA = 33°C/W
TRANSLATOR & CONTROL LOGIC
2.0
÷8
REG
20 19 18 17 16
VDD
1.0
SUFFIX 'S' SUFFIX 'K'
0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150
VBB2
15
Dwg. GP-018-2A
Package Thermal Resistance, RJA A3977xLP ....... 28°C/W* A3977xED ...... 32°C/W A3977xLP ....... 33°C/W
* Measured on JEDEC standard "High-K" four-layer board. Measured on typical two-sided PCB with three square inches (1935 mm2) copper ground area.
Table 1. Microstep Resolution Truth Table MS1 L H L H MS2 L L H H Resolution Full step (2 phase) Half step Quarter step Eighth step
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3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Limits Characteristic Output Drivers Load Supply Voltage Range V BB Operating During sleep mode Output Leakage Current I DSS VOUT = VBB VOUT = 0 V Output On Resistance rDS(on) Source driver, IOUT = -2.5 A Sink driver, IOUT = 2.5 A Body Diode Forward Voltage VF Source diode, IF = -2.5 A Sink diode, IF = 2.5 A Motor Supply Current I BB fPWM < 50 kHz Operating, outputs disabled Sleep mode Control Logic Logic Supply Voltage Range Logic Input Voltage VD D VI N ( 1 ) VIN(0) Logic Input Current I IN(1) I IN(0) Maximum STEP Frequency HOME Output Voltage f STEP VOH V OL Blank Time Fixed Off Time t BLANK t off IOH = -200 µA IOL = 200 µA Rt = 56 k, Ct = 680 pF Rt = 56 k, Ct = 680 pF VIN = 0.7VDD VIN = 0.3VDD Operating 3.0 0 . 7 V DD -20 -20 500* 0 . 7 V DD 700 30 5.0 <1.0 <1.0 950 38 5.5 0 . 3 V DD 20 20 0 . 3 V DD 1200 46 V V V µA µA kHz V V ns µs 8.0 0 <1.0 <1.0 0.45 0.36 35 35 20 -20 0.57 0.43 1.4 1.4 8.0 6.0 20 V V µA µA V V mA mA µA Symbol Test Conditions Min. Typ. Max. Units
continued next page ...
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3977 MICROSTEPPPING DMOS DRIVER WITH TRANSLATOR
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted)
Limits Characteristic Control Logic (cont'd) Mixed Decay Trip Point Symbol Test Conditions Min. Typ. Max. VDD ±3.0 ±10 ±5.0 ±5.0 800 2.95 12 10 20 Units V V V µA % % % ns °C °C V V mA mA µA
PFDH 0.6VDD PFDL 0.21VDD Ref. Input Voltage Range VREF Operating 0 Reference Input Current IREF 0 EG VREF = 2 V, Phase Current = 38.27% Gain (Gm) Error VREF = 2 V, Phase Current = 70.71% (note 3) VREF = 2 V, Phase Current = 100.00% Crossover Dead Time tDT SR enabled 100 475 165 Thermal Shutdown Temp. TJ Thermal Shutdown Hysteresis TJ 15 2.45 2.7 UVLO Enable Threshold VUVLO Increasing VDD UVLO Hysteresis VUVLO 0.05 0.10 Logic Supply Current IDD fPWM < 50 kHz Outputs off Sleep mode * Operation at a step frequency greater than the specified minimum value is possible but not warranteed. NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. EG = ([VREF/8] VSENSE)/(VREF/8)
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