|Category||Interface and Interconnect => Line Drivers|
|Description||8-Bit Addressable Dmos Power Driver|
|Company||Allegro Micro Systems, Inc.|
|Datasheet||Download A6817SEP datasheet
|Cross ref.||Similar parts: L6451|
|OUTPUT ENABLE B LOGIC SUPPLY OUTPUT ENABLE A
Intended for use in ink-jet printer applications, the A6817SEP addressable 28-line decoder/driver combines low-power CMOS inputs and logic with 28 high-current, high-voltage bipolar outputs. A 4-to-14 line decoder determines the selected output driver (n) in each 14-driver bank. Two independent output-enable inputs (active low) then provide the final decoding to activate or 2-of-28 outputs (OUTAn and/or OUTBn). Special internal circuitry is programmed at the time of manufacture to adjust the output pulse timing and thereby the energy the device delivers to the ink-jet print head. The DABiC-IV A6817SEP directly replaces the original BiMOS-II A5817SEP in most applications. The CMOS inputs cause minimal loading and are compatible with standard CMOS, PMOS, and NMOS logic. Use with TTL or DTL circuits may require appropriate pull-up resistors to ensure an input logic high. The internal CMOS logic operates from 5 V supply. A CHIP ENABLE function is provided to lock out the drivers during system power up. The 28 bipolar power outputs are open-collector 30 V Darlington drivers capable of sinking mA at ambient temperatures to 85°C. The A6817SEP is furnished a 44-lead plastic chip carrier (quad pack) for minimum-area, surface-mount applications.OUTPUT DRIVER BANK B OUTPUT DRIVER BANK A
Output Voltage, VCE............................. 30 V Logic Supply Voltage, VDD.................. 7.0 V Input Voltage Range, VIN....................... V to VDD 0.3 V Output Current, IC........................... 600 mA Package Power Dissipation, PD..... 2.70 W* Operating Temperature Range, TA................................. to +85°C Storage Temperature Range, TS.............................. to +150°C
I Controlled Characteristics for Ink-Jet Printers I Addressable Data Entry 30 V Minimum V(BR)CEX I CMOS, PMOS, NMOS Compatible Inputs I Low-Power CMOS Logic
Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage when exposed to extremely high static electrical charges.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 853-5000 W Copyright 1997, 2000 Allegro MicroSystems, Inc.
Limits Characteristic Output Drivers Output Leakage Current Output Saturation Voltage ICEX VCE(SAT) VCE 30 V IOUT 450 mA IOUT 400 mA Output Breakdown Voltage Unclamped Inductive Load Current Turn-On Time Fall Time Turn-Off Time Rise Time Control Logic Input Voltage VIN(1) VIN(0) Logic Input Current IIN(1) IIN(0) Input Resistance Supply Current RIN IDD(ON) IDD(OFF) Two Outputs ON All Drivers OFF, All Inputs 0 V, OEA = OEB = VDD VIN 5.0 V VIN mA µA V(BR)CEX tPHL tf tPLH = 56 VCC = 3 µH, = 500 mA, Test Fig. VCC = 39 VCC = 39 VCC = 39 VCC V, RL See Note V ns Symbol Test Conditions Min Typ Max UnitsNote: Device will turn off and meet all specifications after test.
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