Details, datasheet, quote on part number: A6A6812ELW
PartA6A6812ELW
Category
Description
CompanyAllegro Micro Systems, Inc.
DatasheetDownload A6A6812ELW datasheet
  

 

Features, Applications

LOAD SUPPLY SERIAL DATA OUT 20 OUT 19 OUT 18 OUT 17 OUT 16 OUT 15 OUT 14 OUT 13 OUT 12 OUT 11 BLANKING GROUND VBB VDD LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 STROBE CLOCK

The A6812 devices combine a 20-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6812 features an increased data input rate (compared with the older UCN/UCQ5812-F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With 5 V logic supply, they will operate to at least 10 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6809 and A6810 (10 bits), A6811 (12 bits), and A6818 (32 bits). The A6812 output source drivers are npn Darlingtons, capable of sourcing to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Two temperature ranges are available for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. Package styles are provided for through-hole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow these drivers to source 25 mA from all outputs continuously to more than +43C (suffix -LW), +61C (suffix -EP), or +77C (suffix -A).

Logic Supply Voltage, VDD................... 7.0 V Driver Supply Voltage, VBB................... 60 V Continuous Output Current Range, IOUT......................... +15 mA Input Voltage Range, VIN....................... V to VDD 0.3 V Package Power Dissipation, PD........................................ See Graph Operating Temperature Range, TA (Suffix `E').................. to +85C (Suffix `S').................. to +85C Storage Temperature Range, TS............................... to +125C

Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges.

FEATURES

I Controlled Output Slew Rate I Low Output-Saturation Voltages I High-Speed Data Storage I Low-Power CMOS Logic 60 V Minimum and Latches Output Breakdown I Improved Replacements I High Data Input Rate for UCN5812, I PNP Active Pull-Downs and UCQ5812 Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6812SLW.

SERIAL DATA OUT LOGIC SUPPLY LOAD SUPPLY SERIAL DATA OUT20 OUT19 OUT 1

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts (508) 853-5000 Copyright 2000, Allegro MicroSystems, Inc.

CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT
Serial Shift Register Contents Data Clock Input RN X Serial Data Strobe Output Input P3... X
L = Low Logic Level H = High Logic Level X = Irrelevant

 

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